HIGH-SPEED 3.3V
32K x 18 DUAL-PORT
STATIC RAM
.eatures
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 15/20ns (max.)
– Industrial: 20ns (max.)
Low-power operation
– IDT70V37L
Active: 440mW (typ.)
Standby: 660µW (typ.)
Dual chip enables allow for depth expansion without
external logic
IDT70V37 easily expands data bus width to 36 bits or
more using the Master/Slave select when cascading more
than one device
x
x
x
x
PRELIMINARY
IDT70V37L
x
x
x
x
x
x
x
x
x
x
M/S = V
IH
for
BUSY
output flag on Master,
M/S = V
IL
for
BUSY
input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Separate upper-byte and lower-byte controls for multi-
plexed bus and bus matching compatibility
LVTTL-compatible, single 3.3V (±0.3V) power supply
Available in a 100-pin TQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
.unctional Block Diagram
R/
W
L
UB
L
CE
0L
CE
1L
OE
L
LB
L
R/
W
R
UB
R
CE
0R
CE
1R
OE
R
LB
R
I/O
9-17L
I/O
0-8L
BUSY
L
(1,2)
A
14L
A
0L
32Kx18
MEMORY
ARRAY
70V37
15
15
I/O
9-17R
I/O
Control
I/O
Control
I/O
0-8R
BUSY
R
A
14R
A
0R
(1,2)
.
Address
Decoder
Address
Decoder
CE
0L
CE
1L
OE
L
R/W
L
SEM
L
INT
L
(2)
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
0R
CE
1R
OE
R
R/W
R
SEM
R
(2)
INT
R
4851 drw 01
M/S
(1)
NOTES:
1.
BUSY
is an input as a Slave (M/S=V
IL
) and an output when it is a Master (M/S=V
IH
).
2.
BUSY
and
INT
are non-tri-state totem-pole outputs (push-pull).
JANUARY 2002
DSC-4851/2
1
©2002 Integrated Device Technology, Inc.
IDT70V37L
High-Speed 3.3V 32K x 18 Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Description
The IDT70V37 is a high-speed 32K x 18 Dual-Port Static RAM.
The IDT70V37 is designed to be used as a stand-alone 576K-bit
Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM
for 36-bit-or-more word system. Using the IDT MASTER/SLAVE
Dual-Port RAM approach in 36-bit or wider memory system applica-
tions results in full-speed, error-free operation without the need for
additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access
for reads or writes to any location in memory. An automatic power
down feature controlled by the chip enables (either
CE
0
or CE
1
)
permit the on-chip circuitry of each port to enter a very low standby
power mode.
Fabricated using IDT’s CMOS high-performance technology,
these devices typically operate on only 440mW of power.
The IDT70V37 is packaged in a 100-pin Thin Quad Flatpack
(TQFP).
Pin Configurations
(1,2,3)
INDEX
A
9L
A
10L
A
11L
A
12L
A
13L
A
14L
NC
LB
L
UB
L
CE
0L
CE
1L
SEM
L
R/W
L
OE
L
V
CC
GND
I/O
17L
I/O
16L
GND
I/O
15L
I/O
14L
I/O
13L
I/O
12L
I/O
11L
I/O
10L
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
2
74
3
73
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
72
71
70
69
A
8L
A
7L
A
6L
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
GND
V
CC
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
IDT70V37PF
PN100-1
(4)
100-Pin TQFP
Top View
(5)
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
8R
A
9R
A
10R
A
11R
A
12R
A
13R
A
14R
NC
LB
R
UB
R
CE
0R
CE
1R
SEM
R
R/W
R
GND
OE
R
GND
I/O
17R
GND
I/O
16R
I/O
15R
I/O
14R
I/O
13R
I/O
12R
I/O
11R
4851 drw 02
.
NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to ground.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
I/O
9L
I/O
8L
V
CC
I/O
7
L
I/O
6L
I/O
5L
I/O
4L
I/O
3L
I/O
2L
GND
I/O
1L
I/O
0L
GND
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
I/O
6R
V
CC
I/O
7R
I/O
8R
I/O
9R
I/O
10R
2
IDT70V37L
High-Speed 3.3V 32K x 18 Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
CE
0L
, CE
1L
R/W
L
OE
L
A
0L
- A
14L
I/O
0L
- I/O
17L
SEM
L
UB
L
LB
L
INT
L
BUSY
L
Right Port
CE
0R
, CE
1R
R/W
R
OE
R
A
0R
- A
14R
I/O
0R
- I/O
17R
SEM
R
UB
R
LB
R
INT
R
BUSY
R
M/S
V
CC
GND
Names
Chip Enables
Read/Write Enable
Output Enable
Address
Data Input/Output
Semaphore Enable
Upper Byte Select
Lower Byte Select
Interrupt Flag
Busy Flag
Master or Slave Select
Power
Ground
4851 tbl 01
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
T
BIAS
T
STG
I
OUT
Rating
Terminal Voltage
with Respect to GND
Temperature
Under Bias
Storage
Temperature
DC Output Current
Commercial
& Industrial
-0.5 to +4.6
-55 to +125
-65 to +150
50
Unit
V
o
Recommended DC Operating
Conditions
Symbol
V
CC
GND
V
IH
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
3.0
0
2.0
-0.3
(1)
Typ.
3.3
0
____
Max.
3.6
0
V
CC
+0.3
(2)
0.8
Unit
V
V
V
V
4851 tbl 04
C
C
o
V
IL
____
mA
4851 tbl 02
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
TERM
must not exceed Vcc + 0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of V
TERM
> Vcc + 0.3V.
NOTES:
1. V
IL
> -1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed Vcc + 0.3V.
Capacitance
(1)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
(T
A
= +25°C, f = 1.0MHz)
Conditions
(2)
V
IN
= 3dV
V
OUT
= 3dV
Max.
9
10
Unit
pF
pF
4851 tbl 05
Output Capacitance
Maximum Operating Temperature
and Supply Voltage
(1)
Grade
Commercial
Industrial
Ambient
Temperature
(1)
0
O
C to +70
O
C
-40
O
C to +85
O
C
GND
0V
0V
Vcc
3.3V
+
0.3V
3.3V
+
0.3V
4851 tbl 03
NOTES:
1. This parameter is determined by device characterization but is not produc-
tion tested.
2. 3dV represents the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
NOTE:
1. This is the parameter T
A
. This is the "instant on" case temperature.
3
IDT70V37L
High-Speed 3.3V 32K x 18 Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Truth Table I Chip Enable
(1,2)
CE
CE
0
V
IL
L
< 0.2V
V
IH
H
X
>V
CC
-0.2V
X
(3)
CE
1
Mode
Port Selected (TTL Active)
Port Selected (CMOS Active)
Port Deselected (TTL Inactive)
Port Deselected (TTL Inactive)
Port Deselected (CMOS Inactive)
Port Deselected (CMOS Inactive)
4852 tbl 06
V
IH
>V
CC
-0.2V
X
V
IL
X
(3)
<0.2V
NOTES:
1. Chip Enable references are shown above with the actual
CE
0
and CE
1
levels;
CE
is a reference only.
2. 'H' = V
IH
and 'L' = V
IL
.
3. CMOS standby requires 'X' to be either < 0.2V or >V
CC
-0.2V.
Truth Table II Non-Contention Read/Write Control
Inputs
(1)
CE
(2)
H
X
L
L
L
L
L
L
X
R/W
X
X
L
L
L
H
H
H
X
OE
X
X
X
X
X
L
L
L
H
UB
X
H
L
H
L
L
H
L
X
LB
X
H
H
L
L
H
L
L
X
SEM
H
H
H
H
H
H
H
H
X
Outputs
I/O
9-17
High-Z
High-Z
DATA
IN
High-Z
DATA
IN
DATA
OUT
High-Z
DATA
OUT
High-Z
I/O
0-8
High-Z
High-Z
High-Z
DATA
IN
DATA
IN
High-Z
DATA
OUT
DATA
OUT
High-Z
Mode
Deselected: Power-Down
Both Bytes Deselected
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
Outputs Disabled
4851 tbl 07
NOTES:
1. A
0L
— A
14L
≠
A
0R
— A
14R
2. Refer to Truth Table I - Chip Enable.
Truth Table III Semaphore Read/Write Control
(1)
Inputs
(1)
CE
(2)
H
X
H
X
L
L
R/W
H
H
↑
↑
X
X
OE
L
L
X
X
X
X
UB
X
H
X
H
L
X
LB
X
H
X
H
X
L
SEM
L
L
L
L
L
L
Outputs
I/O
9-17
DATA
OUT
DATA
OUT
DATA
IN
DATA
IN
______
I/O
0-8
DATA
OUT
DATA
OUT
DATA
IN
DATA
IN
______
Mode
Read Data in Semaphore Flag
Read Data in Semaphore Flag
Write I/O
0
into Semaphore Flag
Write I/O
0
into Semaphore Flag
Not Allowed
Not Allowed
4851 tbl 08
______
______
NOTES:
1. There are eight semaphore flags written to I/O
0
and read from all the I/Os (I/O
0
-I/O
17
). These eight semaphore flags are addressed by A
0
-A
2
.
2. Refer to Truth Table I -
Chip Enable
.
4
IDT70V37L
High-Speed 3.3V 32K x 18 Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(V
CC
= 3.3V ± 0.3V)
70V37L
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
(1)
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Conditions
V
CC
= 3.6V, V
IN
= 0V to V
CC
CE
(2)
= V
IH
, V
OUT
= 0V to V
CC
I
OL
= +4mA
I
OH
= -4mA
Min.
___
Max.
5
5
0.4
___
Unit
µA
µA
V
V
4851 tbl 09
___
___
2.4
NOTES:
1. At Vcc
<
2.0V, input leakages are undefined.
2. Refer to Truth Table I -
Chip Enable
.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(5)
(V
CC
= 3.3V ± 0.3V)
70V37L15
Com'l Only
Symbol
I
CC
Parameter
Dynamic Operating
Current
(Both Ports Active)
Standby Current
(Both Ports - TTL Level
Inputs)
Standby Current
(One Port - TTL Level
Inputs)
Full Standby Current
(Both Ports - All CMOS
Level Inputs)
Full Standby Current
(One Port - All CMOS
Level Inputs)
Test Condition
CE
= V
IL
, Outputs Disabled
SEM
= V
IH
f = f
MAX
(2)
CE
L
=
CE
R
= V
IH
SEM
R
=
SEM
L
= V
IH
f = f
MAX
(2)
CE
"A"
= V
IL
and
CE
"B"
= V
IH
(4)
Active Port Outputs Disabled,
f=f
MAX
(2)
,
SEM
R
=
SEM
L
= V
IH
Both Ports
CE
L
and
CE
R
> V
CC
- 0.2V,
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V, f = 0
(3)
SEM
R
=
SEM
L
> V
CC
- 0.2V
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(4)
,
SEM
R
=
SEM
L
> V
CC
- 0.2V,
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V,
Active Port Outp uts Disabled , f = f
MAX
(2)
Version
COM'L
IND
COM'L
IND
COM'L
IND
COM'L
IND
COM'L
IND
L
L
L
L
L
L
L
L
L
L
Typ.
(1)
145
___
70V37L20
Com'l
& Ind
Typ.
(1)
135
135
35
35
90
90
0.2
0.2
90
90
Max.
205
220
55
65
140
150
3.0
3.0
135
145
4851 tbl 10
Max.
235
___
Unit
mA
I
SB1
40
___
70
___
mA
I
SB2
100
___
155
___
mA
I
SB3
0.2
___
3.0
___
mA
I
SB4
95
___
150
___
mA
NOTES:
1. V
CC
= 3.3V, T
A
= +25°C, and are not production tested. I
CCDC
= 90mA (Typ.)
2. At f = f
MAX
,
address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/t
RC,
and using “AC Test Conditions" of input levels of GND
to 3V.
3. f = 0 means no address or control lines change.
4. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
5. Refer to Truth Table I - Chip Enable.
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
