U2784B
2200 MHz / 200 MHz Twin PLL
Description
U2784B is a low power twin PLL manufactured with
TEMIC’s advanced UHF process. The maximum operat-
ing frequency is 2200 MHz and 200 MHz respec tively.
It features a wide supply voltage range from 2.7 to 5.5 V.
Prescaler and power down function for both PLL’s is inte-
grated. Applications are DECT, DCS 1800 and WLAN.
Features
D
Very low current consumption (typical 3 V/12 mA)
D
Supply voltage range 2.7 to 5.5 V
D
Maximum input frequency PLL1: 2200 MHz,
PLL2: 200 MHz
Benefits
D
Low current consumption leads to extended talk time
D
Twin PLL saves costs and space
D
One foot print for all TEMIC twin PLL’s saves design-
in time
D
2 pins for separate power down functions
D
Output for PLL lock status
D
Prescaler 64/65 for PLL1 and 8/9 for PLL2
D
SSO-20 package
D
ESD protected according to MIL-STD 833
method 3015 cl. 2
Block Diagram
1
V
S
analog
V
S
digital
DGND
AGND
OSCi
OSCo
4
2
6
15
7
8
Oscillator
Control functions
16 bit latch
Lock
select
10
Lock Port2
Ports
Power
down Test
9
14
20
5I/Port 0
HPD1/Port1
HPD2/Port4
Port3
on / off
divide by 2
12 bit latch 1
12 bit reference divider 1
17 bit latch 1
Phase
detector 1
Charge
pump 1
3
17
CP1
V
Scp
RFi1
5
64 / 65 Prescaler 1
17 bit main divider 1
Clock
Data
Enable
11
3 bit
12
13
Load control
17 bit
Shift register
Pump
bias
19
Iset
12 bit latch 2
12 bit reference divider 2
14 bit latch 2
Phase
detector 2
Charge
pump 2
18
CP2
RFi2
16
8 / 9 Prescaler 2
14 bit main divider 2
95 10611
Figure 6.
TELEFUNKEN Semiconductors
Rev. A2, 29-Jul-96
1 (11)
U2784B
Ordering Information
Extended Type Number
U2784B-BFS
U2784B-BFSG3
Package
SSO20
SSO20
Remarks
Rail, MOQ 830 pcs
Tape and reel, MOQ 4000 pcs
Pin Description
5I/Port 0
V
S
digital
CP 1
V
S
analog
RFi 1
GND
D
OSC
i
OSC
o
HPD1/Port 1
1
2
3
4
5
6
7
8
9
20 Port 3
19 Iset
18 CP 2
17 V
Scp
16 RFi 2
15 GND
A
14 HPD2/Port 4
13 Enable
12 Data
11 Clock
95 9622
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Lock/Port 2 10
Symbol
Function
5I/Port 0 5I – Control input / o.c.output
V
S
digital Power supply digital section
CP 1
Charge pump output of
synthesizer 1
V
S
analog Power supply analog section
RFi 1
RF divider input synthesizer
GND
D
Ground for digital section
OSC
i
Reference oscillator input
OSC
o
Reference oscillator output
HPD 1/ Hardware power down input of
Port 1
synthesizer 1 / o.c.output
Lock/
Lock output / o.c.output /
Port 2
testmode output
Clock
3-wire-bus: serial clock input
Data
3-wire-bus: serial data input
Enable
3-wire-bus: serial enable input
HPD 2/ Hardware power down input of
Port 4
synthesizer 2 / o.c.output
GND
A
Ground for analog section
RFi 2
RF divider input synthesizer 2
V
Scp
Charge pump supply voltage
CP 2
Charge pump output of
synthesizer 2
Iset
Reference pin for charge pump
currents
Port 3
o.c.output
Absolute Maximum Ratings
Supply voltage
Input voltage
Parameters
Pins 2, 4 and 17
Pins 1, 3, 5, 8, 9, 10, 11, 12,
13, 14, 15, 16, 18 and 20
Symbol
V
S
, V
Scp
V
i
T
j
T
stg
Value
6
0 to V
S
125
– 40 to + 125
Unit
V
V
°C
°C
Junction temperature
Storage temperature range
Operating Range
Parameters
Supply voltage
Pins 2, 4 and 17
Ambient temperature range
2 (11)
Symbol
V
S
, V
Scp
T
amb
Value
2.7 to 5.5
– 40 to + 85
Unit
V
°C
TELEFUNKEN Semiconductors
Rev. A2, 29-Jul-96
U2784B
Thermal Resistance
Junction ambient
Parameters
SSO20
Symbol
R
thja
Value
140
Unit
K/W
Electrical Characteristics
T
amb
= 25
_
C, V
S
= 2.7 to 5.5 V, V
Scp
= 5 V, unless otherwise specified
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V
S
= 3 V
V
CP
= 5 V, PLL in lock
condition
I
S
I
CP
12
1
mA
µA
PLL 1
Input voltage
Scaling factor prescaler
Scaling factor main counter
Scaling factor swallow counter
Reference counter
PLL 2
Input voltage
p
g
Scaling factor prescaler
Scaling factor main counter
Scaling factor swallow
Reference counter
Reference oscillator
Recommended crystal
series resistance
External reference input
frequency
f
RFi1
= 400 – 2200 MHz
V
RFi1
S
PSC
S
M
S
S
S
R
V
RFi2
S
PSC
S
M
S
S
S
R
20
5
0
5
40
20
8/9
5
0
5
10
AC coupled sinewave
RF/2 = 0
RF/2 = 1
AC coupled sinewave
OSC
i
1
1
20
40
MHz
mV
RMS
2047
7
4095
200
200
mV
RMS
64/65
2047
63
4095
200
200
mV
RMS
f
RFi2
= 50 MHz
f
RFi2
= 100 – 200 MHz
Parameters
DC Supply
Supply current
Supply current CP
Test conditions
Symbol
Min.
Typ.
Max.
Unit
W
2)
External reference input
OSC
i
100
amplitude
Logic input levels (Clock, Data, Enable, HPD1, HPD2, 5I)
High input level
V
iH
1.5
Low input level
V
iL
0
High input current
I
iH
–5
Low input current
I
iL
–5
Logic output levels (Port 0, 1, 2, 3, 4, Lock)
Leakage current
V
OH
= 5.5 V
I
L
Saturation voltage
I
OL
= 0.5 mA
V
SL
Charge pump output (R
set
= tbd.)
Source current
V
CP
V
Scp
/2
PLL2
–1
5I = L
PLL1 I
source
–0.2
5I = H
PLL1
–1
Sink current
V
CP
V
Scp
/2
PLL2
1
5I = L
PLL1
0.2
I
sink
5I = H
PLL1
1
Leakage current
V
CP
V
Scp
/2
I
L
5
1)
RMS voltage at 50
W
;
2)
OSC is open if an external reference frequency is applied
o
0.4
5
5
10
0.4
V
V
m
A
m
A
m
A
V
mA
x
x
x
mA
nA
"
TELEFUNKEN Semiconductors
Rev. A2, 29-Jul-96
3 (11)
U2784B
Serial Programming Bus
Reference and programmable counters can be
programmed by the 3-wire-bus (Clock, Data and Enable).
After setting enable signal to high condition, the data
status is transfered bit by bit on the rising edge of the clock
signal into the shift register, starting with the MSB-bit.
After the Enable signal returns to low condition the
programmed information is loaded according to the
addressbits (last three bits) into the addressed latch.
Additional leading bits are ignored and there is no check
made the 3-wire-bus remains active and the IC can be
programmed.
Data is entered with the most significant bit first. The
leading bits deliver the divider or control information.
The trailing three bits are the address field. There are six
different addresses used. The trailing address bits are
decoded upon the falling edge of the Enable signal. the
internal Loadpulse is beginning with the falling edge of
the Enable signal and ending with the falling edge of the
Clock signal. Therefore a minimum holdtime
clock-enable t
HCE
is required.
Bit Allocation
MSB
Bit
1
Bit
2
Bit
3
Bit
4
Bit
5
Bit
6
Bit
7
Bit
8
D9
M3
R9
M6
Bit Bit
9
10
data bits
D8
M2
R8
M5
D7
M1
R7
M4
Bit
11
D6
M0
R6
M3
R6
LP
B
Bit
12
D5
S5
R5
M2
R5
LPA
Bit
13
D4
S4
R4
M1
R4
P4
Bit
14
D3
S3
R3
M0
R3
P3
Bit
15
D2
S2
R2
S2
R2
P2
Bit
16
D1
S1
R1
S1
R1
P1
Bit
17
D0
PLL1
S0
PLL1
R0
PLL2
S0
PLL2
R0
LSB
Bit Bit Bit
18
19
20
address bits
A2
0
0
0
1
1
A1
0
1
1
0
0
A0
1
0
1
0
1
D16 D15 D14 D13 D12 D11 D10
PLL1
M10
M9
M8
M7
M6
M5
PLL1
R11
M4
R10
M7
PLL2
M10
M9
M8
PLL2
R11
RF/
2
Test
5IP
TRI
2
R10 R9 R8 R7
TRI PS2 PS1 H2P H1P
1
P0
SP
D1
SP SP
D 5I D 2
1
1
0
Scaling Factors
PGD of PLL1:
These bits are setting the swallow counter S
S
.
S
S
= S0*2
0
+ S1*2
1
+ ... + S4*2
4
+ S5*2
5
allowed scalling factors for S
S
: 0 ... 63, S
S
< S
M
M0 ... M10: These bits are setting the main counter S
M
.
S
M
= M0*2
0
+ M1*2
1
+ ... + M9*2
9
+ M10*2
10
allowed scalling factors for S
M
: 5 ... 2047
Total scalling factor of the programmable counter:
S
PGD
:
Condition: S
S
< S
M
S
PGD
= (64*S
M
) + S
S
S0 ... S5:
PGD of PLL2:
S0 ... S4:
These bits are setting the swallow counter S
S
.
S
S
= S0*2
0
+ S1*2
1
+ S2*2
2
allowed scalling factors for S
S
: 0 ... 7, S
S
< S
M
These bits are setting the main counter S
M
.
S
M
= M0*2
0
+ M1*2
1
+ ... + M9*2
9
+ M10*2
10
allowed scalling factors for S
M
: 5 ... 2047
Total scalling factor of the programmable counter:
Condition: S
S
< S
M
S
PGD
= (8*S
M
) + S
S
M0 ... M9:
S
PGD
:
RFD of PLL1 and PLL2:
R0 ... R11:
These bits are setting the reference counter S
R
.
S
R
= R0*2
0
+ ... + R10*2
10
+ R11*2
11
allowed scalling factors for S
R
: 5 ... 4095
S
RFD
= 2 * S
R
S
RFD
= S
R
RF/2 = 1:
RF/2 = 0:
4 (11)
TELEFUNKEN Semiconductors
Rev. A2, 29-Jul-96
U2784B
Serial Programming Bus
Control Bits:
P0 ... P4:
LPA, LPB:
o.c. output ports (1 = high impedance)
selection of P2 output or locksignal
LPA LPB function of pin 10
0
0
o.c. output P2
0
1
locksignal of synthesizer 2
1
0
locksignal of synthesizer 1
1
1
wiredor locksignal of both synthesizer
selection of P1/4 output or hardware power down input of synthesizer 1/2 (0 = Port / 1 = HPD)
H1P, H2P:
5IP:
selection of P0 output or high current switching input for the charge pump current of synthesizer 1
(0 = Port / 1 = charge pump 1 current switch input)
phase selection of synthesizer 1 and synthesizer 2 (1 = normal / 0 = invers)
PS-PLL1/2 = 1
CP1/2
I
sink
I
source
0
PS-PLL1/2 = 0
CP1/2
I
source
I
sink
0
PS1, PS2:
f
R
> f
P
f
R
< f
P
f
R
= f
P
RF/2: divide by 2 prescaler for reference divider (0 = off / 1 = on)
SPD1, SPD2: software power down bit of synthesizer 1/2 (0 = powerdown / 1 = powerup)
5I:
software switch for the charge pump current of synthesizer 1 (0 = low current / 1 = high current)
TRI1, TRI2: enables tristate for the charge pump of synthesizer 1/2 (0 = normal / 1 = tristate)
TEST: enables counter testmode (0 = disabled / 1 = enabled)
TEST
1
1
1
1
LPA
1
1
0
0
LPB
0
0
1
1
PS1
1
0
x
x
PS2
x
x
1
0
Testsignal at pin 10
RFD1
PGD1
RFD2
PGD2
To operate the software power down mode the following condition must be set: HXP = 0; power up and power down
will be set by SPDX = 1 (on) and SPDX = 0 (off).
To operate the hardware power down mode the following condition must be set: HXP = 1; SPDX = 1; power up and
power down will be set by high and low state at the hardware power down pins 9/14.
High current of charge pump synthesizer 1 is active when 5I = 1 and if 5IP = 1 the charge pump current control input
pin 1 is in high state.
TELEFUNKEN Semiconductors
Rev. A2, 29-Jul-96
5 (11)
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