FM24CL16
16Kb FRAM Serial 3V Memory
Features
16K bit Ferroelectric Nonvolatile RAM
•
Organized as 2,048 x 8 bits
•
Unlimited Read/Write Cycles
•
45 year Data Retention
•
NoDelay™ Writes
•
Advanced High-Reliability Ferroelectric Process
Fast Two-wire Serial Interface
•
Up to 1MHz Maximum Bus Frequency
•
Direct Hardware Replacement for EEPROM
Low Power Operation
•
2.7 - 3.65V Operation
•
75
µA
Active Current (100 kHz) @ 3V
•
1
µA
Standby Current
Industry Standard Configuration
•
Industrial Temperature -40° C to +85° C
•
8-pin “Green”/RoHS SOIC and TDFN Packages
•
TDFN Footprint Conforms to TSSOP-8
•
Grade 3 AEC-Q100 Qualified (SOIC only)
Description
The FM24CL16 is a 16-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or FRAM is
nonvolatile and performs reads and writes like a
RAM. It provides reliable data retention for 45 years
while eliminating the complexities, overhead, and
system level reliability problems caused by EEPROM
and other nonvolatile memories.
Unlike serial EEPROMs, the FM24CL16 performs
write operations at bus speed. No write delays are
incurred. The next bus cycle may commence
immediately without the need for data polling. In
addition, the product offers unlimited write
endurance, orders of magnitude more endurance than
EEPROM. Also, FRAM exhibits much lower power
during writes than EEPROM since write operations
do not require an internally elevated power supply
voltage for write circuits.
These capabilities make the FM24CL16 ideal for
nonvolatile memory applications requiring frequent
or rapid writes. Examples range from data collection
where the number of write cycles may be critical, to
demanding industrial controls where a long write time
can cause data loss. The combination of features
allows the system to write data more frequently, with
less system overhead.
The FM24CL16 is available in an industry standard
8-pin SOIC and DFN packages and uses a two-wire
protocol. The specifications are guaranteed over the
industrial temperature range from -40°C to +85°C.
D
E
D S
N N
E G
M SI
6B
M E
L1
O D
4C
C
2
E W
FM
R E
ve:
T N
ati
O R
ern
N O
Alt
F
Pin Configuration
NC
1
2
3
4
8
7
6
5
VDD
WP
SCL
NC
NC
VSS
SDA
NC
NC
NC
VSS
1
2
3
4
Top View
8
7
6
5
VDD
WP
SCL
SDA
Pin Names
SDA
SCL
WP
VDD
VSS
Function
Serial Data/Address
Serial Clock
Write Protect
Supply Voltage
Ground
Ordering Information
FM24CL16-G
†
FM24CL16-GTR
†
“Green”/RoHS 8-pin SOIC
“Green”/RoHS 8-pin SOIC,
Tape & Reel
FM24CL16-DG
“Green”/RoHS 8-pin TDFN
FM24CL16-DGTR “Green”/RoHS 8-pin TDFN,
Tape & Reel
FM24CL16-S *
8-pin SOIC
FM24CL16-STR * 8-pin SOIC, Tape & Reel
† Grade 3 AEC-Q100 Qualified
* End of life. Last time buy June 2009.
This product conforms to specifications per the terms of the Ramtron
standard warranty. The product has completed Ramtron’s internal
qualification testing and has reached production status.
Rev. 3.5
Feb. 2011
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
www.ramtron.com
Page 1 of 13
FM24CL16 - 16Kb 3V I2C F-RAM
Counter
Address
Latch
256 x 64
FRAM Array
SCL
WP
Pin Description
Pin Name
SDA
SCL
WP
VDD
VSS
NC
D
E
D S
N N
E G
M SI
6B
M E
L1
O D
4C
C
2
E W
FM
R E
ve:
T N
ati
O R
ern
N O
Alt
F
8
SDA
Serial to Parallel
Converter
Data Latch
Control Logic
Figure 1. Block Diagram
Type
I/O
Input
Input
Supply
Supply
-
Pin Description
Serial Data Address: This is a bi-directional data pin for the two-wire interface. It
employs an open-drain output and is intended to be wire-OR’d with other devices on the
two-wire bus. The input buffer incorporates a Schmitt trigger for noise immunity and the
output driver includes slope control for falling edges. A pull-up resistor is required.
Serial Clock: The serial clock input for the two-wire interface. Data is clocked-out on
the falling edge and clocked-in on the rising edge.
Write Protect: When WP is high, the entire array is write-protected. When WP is low,
all addresses may be written. This pin is internally pulled down.
Supply Voltage (3V)
Ground
No connect
Rev. 3.5
Feb. 2011
Page 2 of 13
FM24CL16 - 16Kb 3V I2C F-RAM
Overview
The FM24CL16 is a serial FRAM memory. The
memory array is logically organized as a 2,048 x 8
memory array and is accessed using an industry
standard two-wire interface. Functional operation of
the FRAM is similar to serial EEPROMs. The major
difference between the FM24CL16 and a serial
EEPROM with the same pinout relates to its superior
write performance.
Two-wire Interface
The FM24CL16 employs a bi-directional two-wire
bus protocol using few pins and little board space.
Figure 2 illustrates a typical system configuration
using the FM24CL16 in a microcontroller-based
system. The industry standard two-wire bus is
familiar to many users but is described in this section.
By convention, any device that is sending data onto
the bus is the transmitter while the target device for
this data is the receiver. The device that is controlling
the bus is the master. The master is responsible for
generating the clock signal for all operations. Any
device on the bus that is being controlled is a slave.
The FM24CL16 is always a slave device.
The bus protocol is controlled by transition states in
the SDA and SCL signals. There are four conditions
including Start, Stop, Data bit, and Acknowledge.
Figure 3 illustrates the signal conditions that define
the four states. Detailed timing diagrams are in the
electrical specifications.
Memory Architecture
When accessing the FM24CL16, the user addresses
2,048 locations each with 8 data bits. These data bits
are shifted serially. The 2,048 addresses are accessed
using the two-wire protocol, which includes a slave
address (to distinguish from other non-memory
devices), a row address, and a segment address. The
row address consists of 8-bits that specify one of 256
rows. The 3-bit segment address specifies one of 8
segments within each row. The complete 11-bit
address specifies each byte uniquely.
Most functions of the FM24CL16 either are
controlled by the two-wire interface or handled
automatically by on-board circuitry. The memory is
read or written at the speed of the two-wire bus.
Unlike an EEPROM, it is not necessary to poll the
device for a ready condition since writes occur at bus
speed. That is, by the time a new bus transaction can
be shifted into the part, a write operation is complete.
This is explained in more detail in the interface
section below.
Note that the FM24CL16 contains no power
management circuits other than a simple internal
power-on reset. It is the user’s responsibility to ensure
that V
DD
is within data sheet tolerances to prevent
incorrect operation.
D
E
D S
N N
E G
M SI
6B
M E
L1
O D
4C
C
2
E W
FM
R E
ve:
T N
ati
O R
ern
N O
Alt
F
Microcontroller
SDA
SCL
SDA
SCL
FM24CL16
Other Slave
Device
VDD
Rmin = 1.1 KΩ
Rmax = tR/Cbus
Figure 2. Typical System Configuration
Rev. 3.5
Feb. 2011
Page 3 of 13
FM24CL16 - 16Kb 3V I2C F-RAM
SCL
SDA
Stop
(Master)
Start
(Master)
7
6
0
Data bit Acknowledge
(Transmitter) (Receiver)
Data bits
(Transmitter)
Stop Condition
A stop condition is indicated when the bus master
drives SDA from low to high while the SCL signal is
high. All operations using the FM24CL16 must end
with a Stop condition. If an operation is pending
when a Stop is asserted, the operation will be aborted.
The master must have control of SDA (not a memory
read) in order to assert a Stop condition.
Start Condition
A Start condition is indicated when the bus master
drives SDA from high to low while the SCL signal is
high. All read and write transactions begin with a
Start condition. An operation in progress can be
aborted by asserting a Start condition at any time.
Aborting an operation using the Start condition will
prepare the FM24CL16 for a new operation.
If during operation the power supply drops below the
specified VDD minimum, the system should issue a
Start condition prior to performing another operation.
Data/Address Transfer
All data transfers (including addresses) take place
while the SCL signal is high. Except under the two
conditions described above, the SDA signal should
not change while SCL is high. For system design
considerations, keeping SCL in a low state while idle
improves robustness.
Acknowledge
The Acknowledge takes place after the 8
th
data bit has
been transferred in any transaction. During this state,
the transmitter should release the SDA bus to allow
the receiver to drive it. The receiver drives the SDA
signal low to acknowledge receipt of the byte. If the
receiver does not drive SDA low, the condition is a
No-Acknowledge and the operation is aborted.
D
E
D S
N N
E G
M SI
6B
M E
L1
O D
4C
C
2
E W
FM
R E
ve:
T N
ati
O R
ern
N O
Alt
F
Figure 3. Data Transfer Protocol
The receiver would fail to acknowledge for two
distinct reasons. First is that a byte transfer fails. In
this case, the No-Acknowledge ends the current
operation so that the part can be addressed again.
This allows the last byte to be recovered in the event
of a communication error.
Second and most common, the receiver does not
acknowledge to deliberately end an operation. For
example, during a read operation, the FM24CL16
will continue to place data onto the bus as long as
the receiver sends Acknowledges (and clocks).
When a read operation is complete and no more data
is needed, the receiver must not acknowledge the
last byte. If the receiver acknowledges the last byte,
this will cause the FM24CL16 to attempt to drive the
bus on the next clock while the master is sending a
new command such as a Stop.
Slave Address
The first byte that the FM24CL16 expects after a
Start condition is the slave address. As shown in
Figure 4, the slave address contains the device type,
the page of memory to be accessed, and a bit that
specifies if the transaction is a read or a write.
Bits 7-4 are the device type and should be set to
1010b for the FM24CL16. The device type allows
other types of functions to reside on the 2-wire bus
within an identical address range. Bits 3-1 are used
for page select. They specify the 256-byte block of
memory that is targeted for the current operation. Bit
0 is the read/write bit. R/W=1 indicates a read
operation and R/W=0 indicates a write operation.
Rev. 3.5
Feb. 2011
Page 4 of 13
FM24CL16 - 16Kb 3V I2C F-RAM
Page
Select
Slave ID
Memory Operation
The FM24CL16 is designed to operate in a manner
very similar to other 2-wire interface memory
products. The major differences result from the
higher performance write capability of FRAM
technology. These improvements result in some
differences between the FM24CL16 and a similar
configuration EEPROM during writes. The complete
operation for both writes and reads is explained
below.
Write Operation
All writes begin with a slave ID then a word address
as previously mentioned. The bus master indicates a
write operation by setting the LSB of the Slave
Address to a 0. After addressing, the bus master
sends each byte of data to the memory and the
memory generates an acknowledge condition. Any
number of sequential bytes may be written. If the
end of the address range is reached internally, the
address counter will wrap from 7FFh to 000h.
Unlike other nonvolatile memory technologies, there
is no write delay with FRAM. The entire memory
cycle occurs in less time than a single bus clock.
Therefore, any operation including read or write can
occur immediately following a write. Acknowledge
polling, a technique used with EEPROMs to
determine if a write is complete is unnecessary and
will always return a ‘ready’ condition.
1
0
1
0
A2
A1
A0
R/W
Figure 4. Slave Address
Word Address
After the FM24CL16 (as receiver) acknowledges the
slave ID, the master will place the word address on
the bus for a write operation. The word address is the
lower 8-bits of the address to be combined with the 3-
bits of the page select to specify the exact byte to be
written. The complete 11-bit address is latched
internally.
No word address occurs for a read operation, though
the 3-bit page select is latched internally. Reads
always use the lower 8-bits that are held internally in
the address latch. That is, reads always begin at the
address following the previous access. A random read
address can be loaded by doing a write operation as
explained below.
After transmission of each data byte, just prior to the
acknowledge, the FM24CL16 increments the internal
address latch. This allows the next sequential byte to
be accessed with no additional addressing. After the
last address (7FFh) is reached, the address latch will
roll over to 000h. There is no limit on the number of
bytes that can be accessed with a single read or write
operation.
Data Transfer
After all address information has been transmitted,
data transfer between the bus master and the
FM24CL16 can begin. For a read operation the
device will place 8 data bits on the bus then wait for
an acknowledge. If the acknowledge occurs, the next
sequential byte will be transferred. If the
acknowledge is not sent, the read operation is
concluded. For a write operation, the FM24CL16 will
accept 8 data bits from the master then send an
acknowledge. All data transfer occurs MSB (most
significant bit) first.
D
E
D S
N N
E G
M SI
6B
M E
L1
O D
4C
C
2
E W
FM
R E
ve:
T N
ati
O R
ern
N O
Alt
F
An actual memory array write occurs after the 8
th
data bit is transferred. It will be complete before the
acknowledge is sent. Therefore, if the user desires to
abort a write without altering the memory contents,
this should be done using start or stop condition
prior to the 8
th
data bit. The FM24CL16 needs no
page buffering.
The memory array can be write protected using the
WP pin. Setting the WP pin to a high condition
(VDD) will write-protect all addresses. The
FM24CL16 will not acknowledge data bytes that are
written to protected addresses. In addition, the
address counter will not increment if writes are
attempted to these addresses. Setting WP to a low
state (VSS) will deactivate this feature.
Figure 5 and 6 below illustrates both a single-byte
and multiple-byte writes.
Rev. 3.5
Feb. 2011
Page 5 of 13
实时操作系统RTOS
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
