C0G (NP0) Dielectric
General Specifications
C0G (NP0) is the most popular formulation of the
“temperature-compensating,” EIA Class I ceramic
materials. Modern C0G (NP0) formulations contain
neodymium, samarium and other rare earth oxides.
C0G (NP0) ceramics offer one of the most stable capacitor
dielectrics available. Capacitance change with temperature
is 0 ±30ppm/°C which is less than ±0.3% C from -55°C
to +125°C. Capacitance drift or hysteresis for C0G (NP0)
ceramics is negligible at less than ±0.05% versus up to
±2% for films. Typical capacitance change with life is less
than ±0.1% for C0G (NP0), one-fifth that shown by most
other dielectrics. C0G (NP0) formulations show no aging
characteristics.
PART NUMBER (see page 2 for complete part number explanation)
0805
Size
(L" x W")
5
Voltage
6.3V = 6
10V = Z
16V = Y
25V = 3
50V = 5
100V = 1
200V = 2
500V = 7
A
Dielectric
C0G (NP0) = A
101
Capacitance
Code (In pF)
2 Sig. Digits +
Number of
Zeros
J
Capacitance
Tolerance
±.10 pF (<10pF)
±.25 pF (<10pF)
±.50 pF (<10pF)
±1% (≥ 10 pF)
±2% (≥ 10 pF)
±5%
±10%
A
Failure
Rate
A = Not
Applicable
T
Terminations
T = Plated Ni
and Sn
Contact
Factory For
1 = Pd/Ag Term
7 = Gold Plated
NOT RoHS
COMPLIANT
2
Packaging
2 = 7" Reel
4 = 13" Reel
U = 4mm TR
(01005)
A
Special
Code
A = Std.
Product
B
C
D
F
G
J
K
=
=
=
=
=
=
=
Contact Factory
For Multiples
NOTE: Contact factory for availability of Termination and Tolerance Options for Specific Part Numbers.
Contact factory for non-specified capacitance values.
Insulation Resistance (Ohm-Farads)
Temperature Coefficient
Typical Capacitance Change
Envelope: 0
±
30 ppm/°C
Capacitance vs. Frequency
+2
Insulation Resistance vs Temperature
10,000
Capacitance
Capacitance
+1
0
-1
-2
1,000
+0.5
0
-0.5
100
%
%
-55 -35 -15 +5 +25 +45 +65 +85 +105 +125
1KHz
10 KHz
100 KHz
1 MHz
10 MHz
0
0
20
40
60
80
100
Temperature
°C
Variation of Impedance with Cap Value
Impedance vs. Frequency
0805 - C0G (NP0)
10 pF vs. 100 pF vs. 1000 pF
100,000
Frequency
Variation of Impedance with Chip Size
Impedance vs. Frequency
1000 pF - C0G (NP0)
10
1206
0805
1812
1210
1.0
Temperature
°C
Variation of Impedance with Ceramic Formu
Impedance vs. Frequency
1000 pF - C0G (NP0) vs X7R
0805
10.00
X7R
NPO
10,000
100
10.0
10 pF
Impedance,
1000
Impedance,
1,000
Impedance,
1.00
0.10
1.0
0.1
1
10
100
100 pF
1000 pF
1000
0.1
10
100
Frequency, MHz
0.01
10
100
1000
Frequency, MHz
Frequency, MHz
4
041816
C0G (NP0) Dielectric
Specifications and Test Methods
Parameter/Test
Operating Temperature Range
Capacitance
Q
Insulation Resistance
Dielectric Strength
NP0 Specification Limits
-55ºC to +125ºC
Within specified tolerance
<30 pF: Q≥ 400+20 x Cap Value
≥30 pF: Q≥ 1000
100,000MΩ or 1000MΩ - μF,
whichever is less
No breakdown or visual defects
Measuring Conditions
Temperature Cycle Chamber
Freq.: 1.0 MHz ± 10% for cap ≤ 1000 pF
1.0 kHz ± 10% for cap > 1000 pF
Voltage: 1.0Vrms ± .2V
Charge device with rated voltage for
60 ± 5 secs @ room temp/humidity
Charge device with 300% of rated voltage for
1-5 seconds, w/charge and discharge current
limited to 50 mA (max)
Note: Charge device with 150% of rated
voltage for 500V devices.
Deflection: 2mm
Test Time: 30 seconds
1mm/sec
Resistance to
Flexure
Stresses
Appearance
Capacitance
Variation
Q
Insulation
Resistance
No defects
±5% or ±.5 pF, whichever is greater
Meets Initial Values (As Above)
≥ Initial Value x 0.3
≥ 95% of each terminal should be covered
with fresh solder
No defects, <25% leaching of either end terminal
≤ ±2.5% or ±.25 pF, whichever is greater
Meets Initial Values (As Above)
Meets Initial Values (As Above)
Meets Initial Values (As Above)
No visual defects
≤ ±2.5% or ±.25 pF, whichever is greater
Meets Initial Values (As Above)
Meets Initial Values (As Above)
Meets Initial Values (As Above)
No visual defects
≤ ±3.0% or ± .3 pF, whichever is greater
≥ 30 pF:
≥10 pF, <30 pF:
<10 pF:
Q≥ 350
Q≥ 275 +5C/2
Q≥ 200 +10C
90 mm
Solderability
Appearance
Capacitance
Variation
Resistance to
Solder Heat
Q
Insulation
Resistance
Dielectric
Strength
Appearance
Capacitance
Variation
Q
Insulation
Resistance
Dielectric
Strength
Appearance
Capacitance
Variation
Q
(C=Nominal Cap)
Insulation
Resistance
Dielectric
Strength
Appearance
Capacitance
Variation
Load
Humidity
Q
Insulation
Resistance
Dielectric
Strength
Dip device in eutectic solder at 230 ± 5ºC
for 5.0 ± 0.5 seconds
Dip device in eutectic solder at 260ºC for 60
seconds. Store at room temperature for 24 ± 2
hours before measuring electrical properties.
Step 1: -55ºC ± 2º
Step 2: Room Temp
Step 3: +125ºC ± 2º
Step 4: Room Temp
30 ± 3 minutes
≤ 3 minutes
30 ± 3 minutes
≤ 3 minutes
Thermal
Shock
Repeat for 5 cycles and measure after
24 hours at room temperature
Load Life
Charge device with twice rated voltage in
test chamber set at 125ºC ± 2ºC
for 1000 hours (+48, -0).
Remove from test chamber and stabilize at
room temperature for 24 hours
before measuring.
≥ Initial Value x 0.3 (See Above)
Meets Initial Values (As Above)
No visual defects
≤ ±5.0% or ± .5 pF, whichever is greater
≥ 30 pF:
≥10 pF, <30 pF:
<10 pF:
Q≥ 350
Q≥ 275 +5C/2
Q≥ 200 +10C
Store in a test chamber set at 85ºC ± 2ºC/
85% ± 5% relative humidity for 1000 hours
(+48, -0) with rated voltage applied.
Remove from chamber and stabilize at
room temperature for 24 ± 2 hours
before measuring.
≥ Initial Value x 0.3 (See Above)
Meets Initial Values (As Above)
041816
5
FPGA/CPLD
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