EMIF02-USB02F2
2-line IPAD™, EMI filter with ESD protection
Features
■
■
■
■
■
■
■
■
2-line low-pass filter + ESD protection
High efficiency in EMI filtering
Lead-free package
Very low PCB space occupation < 3.2 mm
2
Very thin package: 0.65 mm
High efficiency in ESD suppression
High reliability offered by monolithic integration
High reduction of parasitic elements through
integration and wafer level packaging
Figure 1.
Flip Chip
(10 bumps)
Complies with the following standards:
■
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(s
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b
ct
Application
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ro
s)
t(
Description
P
te
uc
le
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od
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s
P
b
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te
le
so
b
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■
IEC 61000-4-2
– 15 kV (air discharge)
– 8 kV (contact discharge)
b
O
so
te
le
4
I4
I3
Pin layout (bump side)
3
2
1
V
CC
ro
P
I6
uc
d
A
B
C
D
s)
t(
MIL STD 883E - Method 3015-6 Class 3
te
le
D1
O2
r
P
I5
GND
od
I2
I1
s)
t(
uc
E
O1
Figure 2.
I6
I5
I4
Basic cell configuration
V
CC
R3 1.3kΩ
R2 33Ω
I2
O2
EMI filtering and ESD protection for USB port.
The EMIF02-USB02F2 is a highly integrated array
designed to suppress EMI / RFI noise for a USB
port. The EMIF02-USB02F2 Flip Chip packaging
means the package size is equal to the die size.
Additionally, this filter includes ESD protection
circuitry which prevents damage to the application
when subjected to ESD surges up to 15 kV.
R4 10kΩ
I3
25pF
25pF
GND
25pF
25pF
R1 33Ω
I1
O1
GND
April 2008
Rev 2
1/7
www.st.com
7
Characteristics
EMIF02-USB02F2
1
Characteristics
Table 1.
Symbol
V
PP
T
j
T
op
T
stg
Absolute ratings (T
amb
= 25 °C)
Parameter and test conditions
ESD discharge IEC 61000-4-2, air discharge
ESD discharge IEC 61000-4-2, contact discharge
Junction temperature
Operating temperature range
Storage temperature range
Value
15
8
125
- 40 to + 85
- 55 to + 150
Unit
kV
°C
°C
Table 2.
Symbol
V
BR
I
RM
V
RM
V
CL
R
d
Electrical characteristics (T
amb
= 25 °C)
Parameter
Breakdown voltage
Leakage current @ V
RM
Stand-off voltage
I
te
le
od
o
r
s
P
b
O
te
le
)-
(s
so
b
ct
u
d
-O
ro
s)
P
t(
te
uc
le
o
od
r
s
P
b
O
te
le
so
b
O
Clamping voltage
V
CL
V
BR
V
RM
I
R
I
RM
ro
P
I
PP
I
RM
I
R
I
PP
uc
d
s)
t(
V
°C
Dynamic impedance
Peak pulse current
V
RM
V
BR
V
CL
s)
t(
uc
I
PP
R
I/O
Series resistance between input
and output
Input capacitance per line
C
line
Symbol
V
BR
I
RM
Test conditions
Min.
6
Typ.
Max.
Unit
V
I
R
= 1 mA
V
RM
= 3V
@ 0V
0.1
0.5
50
µA
pF
Ω
kΩ
kΩ
V
C
line
R
1
,R
2
R
3
R
4
V
F
Tolerance ± 5%
Tolerance ± 5%
33
1.3
10
1
Tolerance ± 5%
@ 1 mA (D1 diode)
2/7
EMIF02-USB02F2
Characteristics
Figure 3.
0.00
dB
- 5.00
- 10.00
- 15.00
Attenuation measurement
Figure 4.
0.00
dB
Analog crosstalk measurement
(I1- O2)
- 10.00
- 20.00
- 30.00
- 20.00
- 40.00
- 25.00
- 30.00
- 35.00
- 40.00
- 45.00
- 50.00
100.0k
1.0M
10.0M
f/Hz
100.0M
1.0G
- 50.00
- 60.00
- 70.00
- 80.00
- 90.00
100.0k
1.0M
10.0M
f/Hz
100.0M
1.0G
Figure 5.
ESD response to IEC 61000-4-2
(+15kV contact discharge)
Figure 6.
Line capacitance versus reverse
applied voltage
C(pF)
40
35
)-
(s
so
b
ct
u
d
-O
ro
s)
P
t(
te
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od
r
s
P
b
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te
le
so
b
O
15
10
0
b
O
so
25
20
30
te
le
0.5
1
ro
P
V
R
(V)
2.5
3
uc
d
s)
t(
P
te
le
1.5
2
od
r
s)
t(
uc
4
4.5
5
3.5
3/7
Application information
EMIF02-USB02F2
2
Application information
Figure 7.
Aplac model of D+ & D- cells
C1
650
650
A3
0.8pF
+
+
Csub
rsub_1k3
+
Csub
rsub_1k3
+
Csub
+
0.8pF
D2
bulk
C1 or E1
16.5
16.5
C3 or E3
50pH
Cbump
I/O
0.8pF
MODEL = D02_usb
+
+
Csub
rsub_33R
+
Csub
rsub_33R
+
Csub
+
0.8pF
MODEL = D02_usb
+
Rbump
bulk
50m
100m
D2
MODEL = D02_usb
MODEL = D02_5p
MODEL = D02_5p
MODEL = D02_usb
bulk
Rsub_D
Rsub_D
D2
bulk
D2
Figure 8.
Aplac model parameters
Cz 17pF opt
Ls 0.4nH
Rs 0.1
Rsub_D 10
Csub 0.3pF
Rsub_33R 16
Rsub_1k3 18
lhole 170pH opt
Cbump 1.2pF opt
Rbump 350
)-
(s
so
b
ct
u
d
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ro
s)
P
t(
3
Ordering information scheme
te
uc
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P
b
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b
O
Figure 9.
Ordering information scheme
EMI Filter
Number of lines
Information
x = resistance value (Ohms)
z = capacitance value / 10(pF)
or
3 letters = application
2 digits = version
Package
F = Flip-Chip
x 2: Lead free, pitch = 500 µm, bump = 315 µm
D02_usb diodes model
+ BV = 7
+ IBV = 1m
+ CJO = Cz
+ M = 0.3333
+ RS = 2
+ VJ = 0.6
+ TT = 100n
b
O
so
te
le
r
P
d
o
uc
s)
t(
Lhole
100m
P
te
le
D02_5p diodes model
+ BV = 100
+ IBV = 1m
+ CJO = 5p
+ M = 0.3333
+ RS = 2
+ VJ = 0.6
+ TT = 100n
od
r
s)
t(
uc
EMIF
yy
-
xxx zz
Fx
4/7
EMIF02-USB02F2
Package information
4
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK
®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the inner box label, in compliance with JEDEC
Standard JESD97. The maximum ratings related to soldering conditions are also marked on
the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at
www.st.com.
Figure 10. Flip Chip package dimensions
700µm ± 50
315µm ± 50
650µm ± 65
495µm ± 50
1.97mm ± 50µm
495µm ± 50
285 µm
)-
(s
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b
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1.62mm ± 50µm
Figure 11. Footprint recommendations
Copper pad Diameter:
250 µm recommended, 300 µm max.
Solder stencil opening:
330 µm recommended
Figure 12. Marking
Dot, ST logo
xx = marking
z = manufacturing location
yww = datecode
(y = year
ww = week)
285 µm
b
O
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ro
P
uc
d
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t(
P
te
le
od
r
s)
t(
uc
E
Solder mask opening recommendation:
340 µm min. for 300 µm copper pad diameter
x x z
y ww
5/7
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