PUSB3F96
10
ESD protection for ultra high-speed interfaces
Rev. 3 — 29 September 2014
Product data sheet
1. Product profile
1.1 General description
The device is designed to protect high-speed interfaces such as SuperSpeed USB,
High-Definition Multimedia Interface (HDMI), DisplayPort, external Serial Advanced
Technology Attachment (eSATA) and Low Voltage Differential Signaling (LVDS) interfaces
against ElectroStatic Discharge (ESD).
The device includes four high-level ESD protection diode structures for ultra high-speed
signal lines and is encapsulated in a leadless small DFN2510A-10 (SOT1176-1) plastic
package.
All signal lines are protected by a special diode configuration offering ultra low line
capacitance of only 0.5 pF. These diodes utilize a unique snap-back structure in order to
provide protection to downstream components from ESD voltages up to
10
kV contact
exceeding IEC 61000-4-2, level 4.
XS
ON
1.2 Features and benefits
System ESD protection for USB 2.0 and SuperSpeed USB 3.0, HDMI 2.0, DisplayPort,
eSATA and LVDS
All signal lines with integrated rail-to-rail clamping diodes for downstream
ESD protection of
10
kV exceeding IEC 61000-4-2, level 4
Matched 0.5 mm trace spacing
Signal lines with
0.05 pF matching capacitance between signal pairs
Line capacitance of only 0.5 pF for each channel
Design-friendly ‘pass-through’ signal routing
1.3 Applications
The device is designed for high-speed receiver and transmitter port protection:
TVs and monitors
DVD recorders and players
Notebooks, main board graphic cards and ports
Set-top boxes and game consoles
NXP Semiconductors
PUSB3F96
ESD protection for ultra high-speed interfaces
2. Pinning information
Table 1.
Pin
1
2
3
4
5
6
7
8
9
10
CH1
CH2
GND
CH3
CH4
n.c.
n.c.
GND
n.c.
n.c.
Pinning
Description
channel 1 ESD protection
channel 2 ESD protection
ground
channel 3 ESD protection
channel 4 ESD protection
not connected
not connected
ground
not connected
not connected
1
2
3
4
5
Transparent top view
10
9
8
7
6
1
2
4
5
Symbol
Simplified outline
Graphic symbol
3, 8
018aaa001
3. Ordering information
Table 2.
Ordering information
Package
Name
PUSB3F96
DFN2510A-10
Description
Version
plastic extremely thin small outline package;
SOT1176-1
no leads; 10 terminals; body 1
2.5
0.5 mm
Type number
4. Marking
Table 3.
PUSB3F96
Marking codes
Marking code
96
Type number
5. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
I
V
ESD
Parameter
input voltage
electrostatic discharge
voltage
IEC 61000-4-2, level 4
contact discharge
air discharge
T
amb
T
stg
[1]
[1]
Conditions
Min
0.5
10
15
40
55
Max
+5.5
+10
+15
+85
+125
Unit
V
kV
kV
C
C
ambient temperature
storage temperature
All pins to ground.
PUSB3F96
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 3 — 29 September 2014
2 of 15
NXP Semiconductors
PUSB3F96
ESD protection for ultra high-speed interfaces
6. Characteristics
Table 5.
Characteristics
T
amb
= 25
C unless otherwise specified.
Symbol
V
BR
I
LR
V
F
C
line
C
line
r
dyn
Parameter
breakdown voltage
reverse leakage current
forward voltage
line capacitance
line capacitance
difference
dynamic resistance
Conditions
I
I
= 1 mA
per channel; V
I
= 3 V
I
I
= 1 mA
f = 1 MHz; V
I
= 3.3 V
f = 1 MHz; V
I
= 3.3 V
surge
positive transient
negative transient
TLP
positive transient
negative transient
V
CL
clamping voltage
I
PP
= 5.2 A
positive transient
I
PP
=
4.4
A
negative transient
[1]
[2]
[3]
This parameter is guaranteed by design.
According to IEC 61000-4-5 (8/20
s
current waveform).
100 ns Transmission Line Pulse (TLP); 50
;
pulser at 80 ns.
[2]
[2]
[3]
[1]
[1]
Min
6
-
-
-
-
Typ
-
-
0.7
0.5
0.05
Max
-
1
-
0.6
-
Unit
V
A
V
pF
pF
[2]
-
-
-
-
-
-
0.41
0.26
0.43
0.28
4.6
2.2
-
-
-
-
-
-
V
V
PUSB3F96
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 3 — 29 September 2014
3 of 15
NXP Semiconductors
PUSB3F96
ESD protection for ultra high-speed interfaces
2
S
dd21
(dB)
-2
aaa-009367
1.2
a
aaa-009368
0.8
-6
0.4
-10
-14
10
6
10
7
10
8
10
9
f (MHz)
10
10
0
0
1
2
3
4
V
I
(V)
5
differential mode
C
line
a
=
---------------------------------
C
line
V
=
0
V
I
Fig 1.
Insertion loss; typical values
Fig 2.
Relative capacitance as a function of input
voltage; typical values
aaa-009370
0
S
dd21
(dB)
-20
aaa-009369
120
Z
dif
(Ω)
110
100
(2)
-40
90
(1)
-60
10
6
10
7
10
8
10
9
f (MHz)
10
10
80
40.0
40.5
41.0
41.5
t (ns)
42.0
Sdd21 normalized to 100
;
differential pairs CH1/CH2 versus CH3/CH4
t
r
= 200 ps; differential pair CH1 + CH2
(1) PUSB3F96 on reference board
(2) Reference board without device under test (DUT)
Fig 3.
Crosstalk; typical values
Fig 4.
Differential Time Domain Reflectometer (TDR)
plot; typical values
PUSB3F96
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 3 — 29 September 2014
4 of 15
NXP Semiconductors
PUSB3F96
ESD protection for ultra high-speed interfaces
aaa-014157
Data rate: 5 Gbit/s
Vertical scale: 166.3 mV/div
Horizontal scale: 20 ps/div
Fig 5.
USB 3.0 eye diagram, Printed-Circuit Board (PCB) with PUSB3F96
aaa-014158
Data rate: 5 Gbit/s
Vertical scale: 166.3 mV/div
Horizontal scale: 20 ps/div
Fig 6.
USB 3.0 eye diagram, PCB without PUSB3F96 (reference)
PUSB3F96
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 3 — 29 September 2014
5 of 15
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