PROTECTION PRODUCTS
Description
RailClamps are surge rated diode arrays designed to
protect high speed data interfaces. The SR series has
been specifically designed to protect sensitive compo-
nents which are connected to data and transmission
lines from overvoltage caused by electrostatic dis-
charge
(ESD),
electrical fast transients
(EFT),
and
lightning.
The unique design of the SR series devices incorpo-
rates eight surge rated, low capacitance steering
diodes and a TVS diode in a single package. During
transient conditions, the steering diodes direct the
transient to either the positive side of the power supply
line or to ground. The internal TVS diode prevents
over-voltage on the power line, protecting any down-
stream components.
The SRV05-4 has a low typical capacitance of 3pF and
operates with virtually no insertion loss to 1GHz. This
makes the device ideal for protection of high-speed
data lines such as USB 2.0, Firewire, DVI, and gigabit
Ethernet interfaces.
The low capacitance array configuration allows the user
to protect four high-speed data or transmission lines.
The low inductance construction minimizes voltage
overshoot during high current surges. They may be
used to meet the ESD immunity requirements of IEC
61000-4-2, Level 4 (±15kV air, ±8kV contact dis-
charge).
RailClamp
Low Capacitance TVS Diode Array
Features
ESD protection for high-speed data lines to
IEC 61000-4-2 (ESD) ±15kV (air), ±8kV (contact)
IEC 61000-4-4 (EFT) 40A (5/50ns)
IEC 61000-4-5 (Lightning) 12A (8/20µs)
Array of surge rated diodes with internal TVS Diode
Small package saves board space
Protects four I/O lines
Low capacitance:
3pF
typical
Low clamping voltage
Low operating voltage: 5.0V
Solid-state silicon-avalanche technology
SRV05-4
Mechanical Characteristics
JEDEC SOT-23 6L package
Molding compound flammability rating: UL 94V-0
Marking : V05
Packaging : Tape and Reel
Applications
USB 2.0 Power and Data Line Protection
Video Graphics Cards
Monitors and Flat Panel Displays
Digital Video Interface (DVI)
10/100/1000 Ethernet
Notebook Computers
SIM Ports
ATM Interfaces
IEEE 1394 Firewire Ports
Circuit Diagram
Schematic and PIN Configuration
5
1
3
4
6
2
SOT-23 6L (Top View)
Revision 01/18/2008
1
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SRV05-4
PROTECTION PRODUCTS
Absolute Maximum Rating
R ating
Peak Pulse Power (tp = 8/20µs)
Peak Pulse Current (tp = 8/20µs)
ESD per IEC 61000-4-2 (Air)
ESD per IEC 61000-4-2 (Contact)
Lead Soldering Temperature
Operating Temperature
Storage Temperature
Symbol
P
p k
I
P P
V
ESD
T
L
T
J
T
STG
Value
300
12
15
8
260 (10 sec.)
-55 to +125
-55 to +150
Units
Watts
A
kV
°C
°C
°C
Electrical Characteristics
SR V05-4
Parameter
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Forward Voltage
Clamping Voltage
Clamping Voltage
Junction Capacitance
Symbol
V
RWM
V
BR
I
R
V
F
V
C
V
C
C
j
Conditions
Pi n 5 to 2
I
t
= 1mA
Pi n 5 to 2
V
RWM
= 5V, T=25°C
Pi n 5 to 2
I
f
= 15mA
I
PP
= 1A, tp = 8/20µs
Any I/O pin to Ground
I
PP
= 5A, tp = 8/20µs
Any I/O pin to Ground
V
R
= 0V, f = 1MHz
Any I/O pin to Ground
V
R
= 0V, f = 1MHz
Between I/O pins
3
1.5
6
5
1.2
12.5
17.5
5
Minimum
Typical
Maximum
5
Units
V
V
µA
V
V
V
pF
pF
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SRV05-4
PROTECTION PRODUCTS
Typical Characteristics
Non-Repetitive Peak Pulse Power vs. Pulse Time
10
110
Power Derating Curve
Peak Pulse Power - P
Pk
(kW)
100
% of Rated Power or
PP
I
90
80
70
60
50
40
30
20
10
0
1
0.1
0.01
0.1
1
10
Pulse Duration - tp (µs)
100
1000
0
25
50
75
100
o
125
150
Ambient Temperature - T
A
( C)
Pulse Waveform
110
100
90
80
70
60
50
40
30
20
10
0
0
5
10
15
Time (µs)
20
25
30
td = I
PP
/2
PP
Clamping Voltage vs. Peak Pulse Current
Waveform
Parameters:
tr = 8µs
td = 20µs
30.00
Clamping Voltage -V
C
(V)
25.00
20.00
15.00
10.00
5.00
0.00
0.00
2.00
4.00
6.00
8.00
10.00
12.00
Peak Pulse Current - I
PP
(A)
Waveform
Parameters:
tr = 8µs
td = 20µs
Percent of I
e
-t
Forward Voltage vs. Forward Current
7.00
Normalized Capacitance vs. Reverse Voltage
1.4
1.2
Forward Voltage -V
F
(V)
6.00
5.00
4.00
3.00
2.00
1.00
0.00
0.00
2.00
4.00
6.00
8.00
10.00
12.00
Forward Current - I
F
(A)
Waveform
Parameters:
tr = 8µs
td = 20µs
C
J
(V
R
) / C
J
(V
R
=0)
1
0.8
0.6
0.4
0.2
f = 1 MHz
0
0
1
2
3
4
5
Reverse Voltage - V
R
(V)
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SRV05-4
PROTECTION PRODUCTS
Applications Information
Insertion Loss S21
CH1
S21
LOG
3 dB/
REF 0 dB
Analog Cross Talk
CH1
S21
LOG
20 dB/
REF 0 dB
START
.030 000 MHz
STOP 3 000 . 000 000 MHz
START
.030 000 MHz
STOP 3 000. 000 000 MHz
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SRV05-4
PROTECTION PRODUCTS
Applications Information
Device Connection Options for Protection of Four
High-Speed Data Lines
The SRV05-4 TVS is designed to protect four data lines
from transient over-voltages by clamping them to a
fixed reference. When the voltage on the protected
line exceeds the reference voltage (plus diode V
F
) the
steering diodes are forward biased, conducting the
transient current away from the sensitive circuitry.
Data lines are connected at pins 1, 3, 4 and 6. The
negative reference (REF1) is connected at pin 2. This
pin should be connected directly to a ground plane on
the board for best results. The path length is kept as
short as possible to minimize parasitic inductance.
The positive reference (REF2) is connected at pin 5.
The options for connecting the positive reference are
as follows:
1. To protect data lines and the power line, connect
pin 5 directly to the positive supply rail (V
CC
). In this
configuration the data lines are referenced to the
supply voltage. The internal TVS diode prevents
over-voltage on the supply rail.
2. The SRV05-4 can be isolated from the power
supply by adding a series resistor between pin 5
and V
CC
. A value of 100kΩ is recommended. The
internal TVS and steering diodes remain biased,
providing the advantage of lower capacitance.
3. In applications where no positive supply reference
is available, or complete supply isolation is desired,
the internal TVS may be used as the reference. In
this case, pin 5 is not connected. The steering
diodes will begin to conduct when the voltage on
the protected line exceeds the working voltage of
the TVS (plus one diode drop).
ESD Protection With RailClamps
RailClamps are optimized for ESD protection using the
rail-to-rail topology. Along with good board layout,
these devices virtually eliminate the disadvantages of
using discrete components to implement this topology.
Consider the situation shown in Figure 1 where dis-
crete diodes or diode arrays are configured for rail-to-
rail protection on a high speed line. During positive
duration ESD events, the top diode will be forward
biased when the voltage on the protected line exceeds
Data Line and Power Supply Protection Using Vcc as
reference
Data Line Protection with Bias and Power Supply
Isolation Resistor
Data Line Protection Using Internal TVS Diode as
Reference
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