EMIF03-SIM01F2
3-line IPAD™, EMI filter including ESD protection
Features
■
■
■
■
■
■
■
■
EMI symmetrical (I/O) low-pass filter
High efficiency in EMI filtering
Lead-free package
Very low PCB space occupation:
1.42 mm x 1.42 mm
Very thin package: 0.65 mm
High efficiency in ESD suppression
High reliability offered by monolithic integration
High reduction of parasitic elements through
integration and wafer level packaging
Figure 1.
Pin layout (bump side)
3
RST
in
Flip Chip
(8 bumps)
2
RST
out
1
A
CLT
out
Complies with the following standards
■
IEC 61000-4-2 level 4 on input pins
– 15 kV (air discharge)
– 8 kV (contact discharge)
MIL SRD 883E - Method 3015-6 Class 3
Figure 2.
V
CC
CLT
in
Gnd
B
C
Data
in
V
CC
Data
out
■
Applications
EMI filtering and ESD protection for:
■
■
Configuration
100
Ω
SIM interface (subscriber identity module)
UIM interface (universal identity module)
RST in
R1
47
Ω
CLK in
R2
100
Ω
Data in
R3
RST out
CLK out
Data out
Description
The EMIF03-SIM01F2 is a highly integrated
device designed to suppress EMI/RFI noise in all
systems subjected to electromagnetic
interference. The EMIF03 Flip Chip packaging
means the package size is equal to the die size.
This filter includes ESD protection circuitry which
prevents damage to the application when
subjected to ESD surges up 15 kV.
Cline = 35pF max.
GND
TM:
IPAD is a trademark of STMicroelectronics.
April 2008
Rev 3
1/7
www.st.com
7
Characteristics
EMIF03-SIM01F2
1
Characteristics
Table 1.
Symbol
T
j
T
op
T
stg
Absolute ratings (limiting values)
Parameter
Maximum junction temperature
Operating temperature range
Storage temperature range
Value
125
-40 to +85
-55 to 150
Unit
°C
°C
°C
Table 2.
Symbol
V
BR
I
RM
V
RM
V
CL
R
d
I
PP
R
I/O
C
line
Symbol
V
BR
I
RM
R
d
R
1
R
2
R
3
C
line
\
Electrical characteristics (T
amb
= 25 °C)
Parameters
Breakdown voltage
Leakage current @ V
RM
Stand-off voltage
Clamping voltage
Dynamic impedance
Peak pulse current
Series resistance between input and
output
Input capacitance per line
Test conditions
I
R
= 1 mA
V
RM
= 3 V per line
1.5
95
44.65
95
@0V
100
47
100
105
49.35
105
35
Min
6
1
Typ
Max
Unit
V
µA
Ω
Ω
Ω
Ω
pF
I
PP
V
CL
V
BR
V
RM
I
RM
I
R
V
F
V
I
F
I
2/7
EMIF03-SIM01F2
Characteristics
Figure 3.
0.00
dB
-5.00
-10.00
-15.00
-20.00
-25.00
-30.00
-35.00
-40.00
-45.00
-50.00
100.0k
S21 (dB) attenuation measurement Figure 4.
Aplac 7.60 User: STMicroelectronics Feb 22 2001
Analog crosstalk measurement
dB
1.0M
10.0M
f/Hz
A3_A2(RST)
100.0M
1.0G
B3_B1(CLK)
C3_C1(DAT)
MHz
Figure 5.
Digital crosstalk measurement
Figure 6.
ESD response to IEC 61000-4-2
(-15 kV air discharge) on one input
(Vin) and on one output (Vout)
V(in1)
V(out1)
Figure 7.
ESD response to IEC 61000-4-2
(+15 kV air discharge) on one input
(Vin) and on one output (Vout)
V(in1)
Figure 8.
Line capacitance versus applied
voltage (typical)
C(pF)
35
30
25
20
F=1MHz
Vosc=30mV
Tj=25°C
V(out1)
15
VR(V)
10
0
1
2
3
4
5
6
3/7
Application information
EMIF03-SIM01F2
2
Application information
Figure 9.
Aplac model
Rseries
Port1
50
MODEL = demif03
MODEL = demif03
Port2
50
sub
sub
Vcc
DEMIF03 diodes Model
- RS = 1.2
- CJO = 17p
- M = 0.3333
- VJ = 0.6
- ISR = 100p
- BV = 6.8
- IBV = 1m
- TT = 100n
50p
0.05
MODEL = demif03_Vcc
0.08nH
Rseries = 47R (CLK line)
= 100R (RST & Data lines)
DEMIF03_Vcc diode Model
- RS = 1.5
- CJO = 20p
- M = 0.3333
- VJ = 0.6
- ISR = 100p
- BV = 6.8
- IBV = 1m
- TT = 100n
sub
0.1
3
Ordering information scheme
Figure 10. Ordering information scheme
EMIF
EMI Filter
Number of lines
Information
x = resistance value (Ohms)
z = capacitance value / 10(pF)
or
3 letters = application
2 digits = version
Package
F = Flip Chip
x = 2: Lead-free, pitch = 500 µm, bump = 315 µm
yy
-
xxx zz
Fx
4/7
EMIF03-SIM01F2
Package information
4
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK
®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the inner box label, in compliance with JEDEC
Standard JESD97. The maximum ratings related to soldering conditions are also marked on
the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at
www.st.com.
Figure 11. Package dimensions
500 µm ± 50
650 µm ± 65
315 µm ± 50
500 µm ± 50
210 µm
1.42 mm ± 50 µm
Figure 12. Footprint
Figure 13. Marking
Dot, ST logo
xx = marking
z = manufacturing
location
yww = datecode
(y = year
ww = week)
Copper pad Diameter:
250 µm recommended, 300 µm max
210 µm
1.42mm ± 50 µm
E
Solder stencil opening: 330 µm
Solder mask opening recommendation:
340 µm min for 315 µm copper pad diameter
x x z
y ww
Figure 14. Flip Chip tape and reel specification
Dot identifying Pin A1 location
4 ± 0.1
Ø 1.5 ± 0.1
1.75 ± 0.1
3.5 ± 0.1
1.52
8 ± 0.3
ST
E
ST
E
ST
E
xxx
yww
xxx
yww
xxx
yww
1.52
0.73 ± 0.05
4 ± 0.1
All dimensions in mm
User direction of unreeling
5/7
传感器
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