CS5101A
CS5102A
16-Bit, 100 kHz / 20 kHz A/D Converters
Features
l
Monolithic
Description
CMOS A/D Converters
The CS5101A and CS5102A are 16-bit monolithic
CMOS analog-to-digital converters capable of 100 kHz
(5101A) and 20 kHz (5102A) throughput. The
CS5102A’s low power consumption of 44 mW, coupled
with a power down mode, makes it particularly suitable
for battery powered operation.
On-chip self-calibration circuitry achieves nonlinearity of
±0.001% of FS and guarantees 16-bit no missing codes
over the entire specified temperature range. Superior lin-
earity also leads to 92 dB S/(N+D) with harmonics below
-100 dB. Offset and full-scale errors are minimized dur-
ing the calibration cycle, eliminating the need for external
trimming.
The CS5101A and CS5102A each consist of a 2-chan-
nel input multiplexer, DAC, conversion and calibration
microcontroller, clock generator, comparator, and serial
communications port. The inherent sampling architec-
ture of the device eliminates the need for an external
track and hold amplifier.
The converters' 16-bit data is output in serial form with ei-
ther binary or 2's complement coding. Three output
timing modes are available for easy interfacing to micro-
controllers and shift registers. Unipolar and bipolar input
ranges are digitally selectable.
ORDERING INFORMATION
See page 36.
-
Inherent Sampling Architecture
-
2-Channel Input Multiplexer
-
Flexible Serial Output Port
l
Ultra-Low
Distortion
-
S/(N+D): 92 dB
-
THD: 0.001%
l
Conversion
Time
-
CS5101A: 8 µs
-
CS5102A: 40 µs
l
Linearity
Error: ±0.001% FS
Maintains Accuracy
-
Guaranteed No Missing Codes
l
Self-Calibration
l
Low
-
Over Time and Temperature
Power Consumption
-
CS5101A: 320 mW
-
CS5102A: 44 mW
-
Power-down Mode: <1 mW
l
Evaluation
Board Available
I
HOLD SLEEPRST STBY CODE BP/UP CRS/FIN TRK1 TRK2 SSH/SDLSDATA
12
28
2
5
16
17
10
8
9
11
15
CLKIN
XOUT
REFBUF
VREF
AIN1
AIN2
CH1/2
AGND
3
4
21
20
19
24
13
22
Clock
Generator
14
Control
Calibration
SRAM
SCLK
-
+
-
+
-
+
25
VA+
23
VA-
Microcontroller
26
TEST
SCKMOD
OUTMOD
16-Bit Charge
Redistribution
DAC
27
-
+
Comparator
18
6
DGND
1
VD-
7
VD+
Cirrus Logic, Inc.
Crystal Semiconductor Products Division
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com
Copyright
©
Cirrus Logic, Inc. 1997
(All Rights Reserved)
MAR ‘95
DS45F2
1
CS5101A
ANALOG CHARACTERISTICS
(T
A
= T
MIN
to T
MAX
;
VA+, VD+ = 5V; VA-, VD- = -5V;
VREF = 4.5V; Full-Scale Input Sinewave, 1 kHz; CLKIN = 4 MHz for -16, 8 MHz for -8; f
s
= 50 kHz for -16,
100 kHz for -8; Bipolar Mode; FRN Mode; AIN1 and AIN2 tied together, each channel tested separately; Analog
Source Impedance = 50
Ω
with 1000 pF to AGND unless otherwise specified)
Parameter*
Specified Temperature Range
Accuracy
Linearity Error
-J,A,S
(Note 1)
-K,B,T
Drift
(Note 2)
Differential Linearity
(Notes 3, 4)
Full Scale Error
-J,A,S
(Note 1)
-K,B,T
Drift
(Note 2)
Unipolar Offset
-J,A,S
-K,B,T
Drift
-J,A,S
-K,B,T
Drift
(Note 1)
(Note 2)
(Note 1)
(Note 2)
CS5101A-J,K
Min Typ Max
0 to +70
-
-
-
16
-
-
-
-
-
-
-
-
-
-
-
-
0.002 0.003
0.001 0.002
-
±
1/4
-
-
±
1
±
4
±
1
±
3
-
±
1
±
2
±
5
±
2
±
4
-
±
1
±
2
±
5
±
2
±
3
-
±
1
±
1
±
1
±
1
±
4
±
3
-
CS5101A-A,B
Min Typ Max
-40 to +85
-
-
-
16
-
-
-
-
-
-
-
-
-
-
-
-
0.002 0.003
0.001 0.002
-
±
1/4
-
-
±
1
±
4
±
1
±
3
-
±
1
±
2
±
5
±
2
±
4
-
±
1
±
2
±
5
±
2
±
3
-
±
2
±
1
±
1
±
1
±
4
±
3
-
CS5101A-S,T
Min Typ Max
-55 to +125
-
-
-
16
-
-
-
-
-
-
-
-
-
-
-
-
Units
°C
Bipolar Offset
0.002 0.004 %FS
0.001 0.003 %FS
-
±
1/2
∆LSB
-
-
Bits
LSB
±
2
±
5
LSB
±
2
±
4
∆LSB
-
±
2
LSB
±
2
±
5
LSB
±
2
±
4
∆LSB
-
±
2
LSB
±
2
±
5
LSB
±
2
±
3
∆LSB
-
±
2
±
1
±
1
±
2
±
5
±
3
-
LSB
LSB
∆LSB
Bipolar Negative Full-Scale Error
-J,A,S
(Note 1)
-K,B,T
Drift
(Note 2)
Dynamic Performance
(Bipolar Mode)
Peak Harmonic or Spurious Noise (Note 1)
1 kHz Input
-J,A,S
-K,B,T
12 kHz Input
-J,A,S
-K,B,T
Total Harmonic Distortion -J,A,S
-K,B,T
Signal-to-Noise Ratio
(Note 1)
0dB Input
-J,A,S
-K,B,T
-60 dB Input
-J,A,S
-K,B,T
Noise
(Note 5)
Unipolar Mode
Bipolar Mode
96
98
85
85
-
-
87
90
-
-
-
-
100
102
88
91
0.002
0.001
90
92
30
32
35
70
-
-
-
-
-
-
-
-
-
-
-
-
96
98
85
85
-
-
87
90
-
-
-
-
100
102
88
91
0.002
0.001
90
92
30
32
35
70
-
-
-
-
-
-
-
-
-
-
-
-
94
98
83
85
-
-
87
90
-
-
-
-
100
102
88
91
0.002
0.001
90
92
30
32
35
70
-
-
-
-
-
-
-
-
-
-
-
-
dB
dB
dB
dB
%
%
dB
dB
dB
dB
µV
rms
µV
rms
Notes: 1. Applies after calibration at any temperature within the specified temperature range. At temp
2. Total drift over specified temperature range after calibration at power-up at 25
°C.
3. Minimum resolution for which no missing codes is guaranteed over the specified temperature range.
4. Clock speeds of less than 1.0 MHz, at temperatures >100°C will degrade DNL performance.
5. Wideband noise aliased into the baseband. Referred to the input.
*Refer to
Parameter Definitions
(immediately following the pin descriptions at the end of this data sheet).
Specifications are subject to change without notice.
2
DS45F2
CS5101A
ANALOG CHARACTERISTICS
Parameter*
Specified Temperature Range
Analog Input
Aperture Time
Aperture Jitter
Input Capacitance
(Note 6)
Unipolar Mode
Bipolar Mode
Conversion & Throughput
Conversion Time
(Note 7)
-8
-16
Acquisition Time
(Note 8)
-8
-16
(Note 9)
-8
-16
(continued)
CS5101A -J,K CS5101A -A,B CS5101A -S,T
Symbol Min Typ Max Min Typ Max Min Typ Max Units
-
0 to +70
40 to +85
55 to +125
°C
-
-
-
-
-
-
-
-
25
100
-
-
-
-
-
-
25
100
-
-
-
-
-
-
25
100
-
-
ns
ps
pF
pF
320 425
200 265
320 425
200 265
320 425
200 265
t
c
tc
-
-
-
-
100
50
-
-
8.12
16.25
-
-
-
-
100
50
-
-
8.12
16.25
-
-
-
-
100
50
-
-
8.12
16.25
µs
µs
µs
µs
kHz
kHz
t
a
ta
- 1.88
2.6 3.75
-
-
-
-
- 1.88
2.6 3.75
-
-
-
-
- 2.88
2.6 3.75
-
-
-
-
Throughput
f
tp
f
tp
Power Supplies
Power Supply Current
(Note 10)
Positive Analog
Negative Analog
(SLEEP High)
Positive Digital
Negative Digital
Power Consumption
(Notes 10, 11)
(SLEEP High)
(SLEEP Low)
Power Supply Rejection:
(Note 12)
Positive Supplies
Negative Supplies
Notes:
I
A
+
I
A
-
I
D
+
I
D
-
P
do
P
ds
PSR
PSR
-
-
-
-
-
-
-
-
21
-21
11
-11
28
-28
15
-15
-
-
-
-
-
-
-
-
21
-21
11
-11
28
-28
15
-15
-
-
-
-
-
-
-
-
21
-21
11
-11
28
-28
15
-15
mA
mA
mA
mA
mW
mW
dB
dB
320 430
1
-
84
84
-
-
320 430
1
-
84
84
-
-
320 430
1
-
84
84
-
-
6. Applies only in the track mode. When converting or calibrating, input capacitance will not exceed 30 pF.
7. Conversion time scales directly to the master clock speed. The times shown are for synchronous,
internal loopback (FRN mode) with 8.0 MHz CLKIN. In PDT, RBT, and SSC modes, asynchronous delay
between the falling edge of HOLD and the start of conversion may add to the apparent conversion time.
This delay will not exceed 1.5 master clock cycles + 10 ns. In PDT, RBT, and SSC modes, CLKIN can
be increased as long as the HOLD sample rate is 100 kHz max.
8. The CS5101A requires 6 clock cycles of coarse charge, followed by a minimum of 1.125
µs
of fine charge.
FRN mode allows 9 clock cycles for fine charge which provides for the minimum 1.125
µs
with an 8 MHz
clock, however; in PDT, RBT, or SSC modes, at clock frequencies of 8 MHz or less, fine charge may
be less than 9 clock cycles. This reflects the typ. specification (6 clock cycles + 1.125
µs).
9. Throughput is the sum of the acquisition and conversion times. It will vary in accordance with conditions
affecting acquisition and conversion times, as described above.
10. All outputs unloaded. All inputs at VD+ or DGND.
11. Power consumption in the sleep mode applies with no master clock applied (CLKIN held high or low).
12. With 300 mV p-p, 1 kHz ripple applied to each supply separately in the bipolar mode. Rejection
improves by 6 dB in the unipolar mode to 90 dB. Figure 23 shows a plot of typical power supply
rejection versus frequency.
3
DS45F2
CS5101A
VA+, VD+ = 5V
±
10%;
VA-, VD- = -5V
±
10%; Inputs: Logic 0 = 0V, Logic 1 = VD+; C
L
= 50 pF)
SWITCHING CHARACTERISTICS
(T
A
= T
MIN
to T
MAX
;
Parameter
CLKIN Period
(Note 4)
-8
-16
Symbol
t
clk
t
clk
t
clkl
t
clkh
(Note 13)
-8
-16
(Note 14)
f
xtal
f
xtal
-
t
rst
t
drrs
t
cal
(Note 15)
(Note 15)
(Note 16)
(Note 16)
(Note 16)
(Note 17)
(Note 16)
(Note 17)
t
drsh1
t
dfsh4
t
dfsh2
t
dfsh1
t
drsh
t
hold
t
dhlri
t
hcf
Min
108
250
37.5
37.5
2.0
2.0
-
150
-
-
-
-
-
66t
clk
-
1t
clk
+20
15
95
Typ
-
-
-
-
-
-
2
-
100
11,528,160
80
-
60
-
120
-
-
-
Max
10,000
10,000
-
-
9.216
4.0
-
-
-
-
-
68t
clk
+260
68t
clk
+260
-
63t
clk
64t
clk
1tclk+10
Units
ns
ns
ns
ns
MHz
MHz
ms
ns
ns
t
clk
ns
ns
ns
ns
ns
ns
ns
ns
CLKIN Low Time
CLKIN High Time
Crystal Frequency
SLEEP Rising to Oscillator Stable
RST Pulse Width
RST to STBY Falling
RST Rising to STBY Rising
CH1/2 Edge to TRK1, TRK2 Rising
CH1/2 Edge to TRK1, TRK2 Falling
HOLD to SSH Falling
HOLD to TRK1, TRK2, Falling
HOLD to TRK1, TRK2, SSH Rising
HOLD Pulse Width
HOLD to CH1/2 Edge
HOLD Falling to CLKIN Falling
Notes: 13. External loading capacitors are required to allow the crystal to oscillate. Maximum crystal frequency
is 8.0 MHz in FRN mode (100 kHz sample rate).
14. With a 8 MHz crystal, two 10 pF loading capacitors and a 10 MΩ parallel resistor (see Figure 8).
15. These times are for FRN mode.
16. SSH only works correctly if HOLD falling edge is within +15 to +30 ns of CH1/2 edge or if CH1/2 edge
occurs after HOLD rises to 64 t
clk
after HOLD has fallen. These times are for PDT and RBT modes.
17. When HOLD goes low, the analog sample is captured immediately. To start conversion, HOLD must
be latched by a falling edge of CLKIN. Conversion will begin on the next rising edge of CLKIN after
HOLD is latched. If HOLD is operated synchronous to CLKIN, the HOLD pulse width may be as
narrow as 150 ns for all CLKIN frequencies if CLKIN falls 95 ns after HOLD falls. This
ensures that the HOLD pulse will meet the minimum specification for t
hcf
.
4
DS45F2
CS5102A
VA+, VD+ = 5V; VA-, VD- = -5V;
VREF = 4.5V; Full-Scale Input Sinewave, 200 Hz; CLKIN = 1.6 MHz; f
s
= 20 kHz; Bipolar Mode; FRN Mode;
AIN1 and AIN2 tied together, each channel tested separately; Analog Source Impedance = 50
Ω
with 1000pF to
AGND unless otherwise specified)
CS5102A-J,K
Parameter*
Specified Temperature Range
Min
Typ
0 to +70
(Note 1)
(Note 2)
(Notes 3, 18)
-J,A,S
-K,B,T
Drift
-J,A,S
-K,B,T
Drift
-J,A,S
-K,B,T
Drift
-J,A,S
-K,B,T
Drift
(Note 1)
(Note 2)
(Note 1)
(Note 2)
(Note 1)
(Note 2)
(Note 1)
(Note 2)
-
-
-
16
-
-
-
-
-
-
-
-
-
-
-
-
0.002 0.003
0.001 0.0015
-
±
1/4
-
±
2
±
2
±
1
±
1
±
1
±
1
±
1
±
1
±
1
±
2
±
2
±
1
100
102
0.002
0.001
90
92
30
32
35
70
-
±
4
±
3
-
±
4
±
3
-
±
4
±
3
-
±
4
±
3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
16
-
-
-
-
-
-
-
-
-
-
-
-
Max
CS5102A-A,B
Min
Typ
Max
CS5102A-S,T
Min
Typ
Max
Units
°C
ANALOG CHARACTERISTICS
(T
A
= T
MIN
to T
MAX
;
-40 to +85
0.002 0.003
0.001 0.0015
-
±
1/4
-
±
2
±
2
±
1
±
1
±
1
±
1
±
1
±
1
±
2
±
2
±
2
±
2
100
102
0.002
0.001
90
92
30
32
35
70
-
±
4
±
3
-
±
4
±
3
-
±
4
±
3
-
±
4
±
3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-55 to +125
Accuracy
Linearity Error
-J,A,S
-K,B,T
Drift
0.002 0.004 %FS
0.001 0.002 %FS
-
±
1/2
∆LSB
-
±
2
±
2
±
2
±
1
±
1
±
2
±
1
±1
±
2
±
2
±
2
±
2
100
102
0.002
0.001
90
92
30
32
35
70
-
±
5
±
3
-
±
5
±
3
-
±
5
±
3
-
±
5
±
3
-
-
-
-
-
-
-
-
-
-
-
Bits
LSB
LSB
∆LSB
LSB
LSB
∆LSB
LSB
LSB
∆LSB
LSB
LSB
∆LSB
dB
dB
%
%
dB
dB
dB
dB
µV
rms
µV
rms
Differential Linearity
Full Scale Error
16
-
-
-
-
-
-
-
-
-
-
-
-
Unipolar Offset
Bipolar Offset
Bipolar Negative
Full-Scale Error
Dynamic Performance
Peak Harmonic or
Spurious Noise
(Bipolar Mode)
(Note 1)
96
98
-
-
(Note 1)
87
90
-
-
-
-
87
90
-
-
-
-
87
90
-
-
-
-
96
98
-
-
94
98
-
-
-J,A,S
-K,B,T
Total Harmonic Distortion -J,A,S
-K,B,T
Signal-to-Noise Ratio
0dB Input
-J,A,S
-K,B,T
-60 dB Input
-J,A,S
-K,B,T
Noise
(Note 5)
Unipolar Mode
Bipolar Mode
Note: 18. Clock speeds of less than 1.6 MHz, at temperatures >100°C will degrade DNL performance.
*Refer to
Parameter Definitions
(immediately following the pin descriptions at the end of this data sheet).
Specifications are subject to change without notice.
DS45F2
5
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