COM20051
Integrated Microcontroller and
ARCNET (ANSI 878.1) Interface
FEATURES
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High Performance/Low Cost
Microcontroller Based on Popular 8051
Architecture
Intel
8051 Instruction Set Compatible
Drop-In Replacement for 80C32 PLCC
Network Supports up to 255 Nodes
Powerful Network Diagnostics
Maximum 507 Byte Packets
Duplicate Node ID Detection
Self-Configuring Network Protocol
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Retains all 8051 Peripherals Including Serial
I/O and Two Timers
Utilizes ARCNET Token Bus Network
Engine
Requires No Special Emulators
5 Mbps to 156 Kbps Network Data Rate
Network Interface Supports RS-485, Twisted
Pair, Coaxial, and Fiber Optic Interfaces
Receive All Mode Allows Any Packet to Be
Received
GENERAL DESCRIPTION
The COM20051 is a low-cost, highly-integrated
microcontroller incorporating a high-performance
network controller based on the ARCNET Token
Bus Standard (ANSI 878.1). The COM20051 is
based around the popular Intel 8051
architecture. The device is implemented using a
microcontroller core compatible with the Intel
80C32 ROMless version of the 8051
architecture.
The COM20051 is ideal for
distributed control networking applications such
as those found in industrial/machine controls,
building/factory automation, consumer products,
instrumentation and automobiles.
The COM20051 contains many features that are
beneficial for embedded control applications.
The microcontroller is a fully-functional 16MHz
80C32 that is comparable to the Intel 80C32 with
2 timers. In contrast
to other embedded
controller/networking solutions, the COM20051
adds a fully-featured, robust, powerful, and
simple network interface while retaining all of the
basic 8051 peripherals, such as the serial port
and counter/timers.
In addition, the COM20051 supports an
Emulation Mode that permits the use of a
standard 80C32 emulator in conjunction with the
COM20051 to develop software drivers for the
network core.
ARCNET core is mapped to a
256-byte page of the External Data Memory
Space
of
the
80C32.
This
TABLE OF CONTENTS
FEATURES........................................................................................................................................................................1
GENERAL DESCRIPTION................................................................................................................................................1
PIN CONFIGURATION......................................................................................................................................................3
OVERVIEW........................................................................................................................................................................4
DESCRIPTION OF PIN FUNCTIONS...............................................................................................................................4
BASIC ARCHITECTURE...................................................................................................................................................7
PROTOCOL DESCRIPTION...........................................................................................................................................12
NETWORK PROTOCOL ..................................................................................................................................................12
DATA RATES....................................................................................................................................................................12
NETWORK RECONFIGURATION...................................................................................................................................12
BROADCAST MESSAGES ..............................................................................................................................................14
EXTENDED TIMEOUT FUNCTION.................................................................................................................................14
LINE PROTOCOL.............................................................................................................................................................15
SYSTEM DESCRIPTION .................................................................................................................................................18
MICROCONTROLLER INTERFACE ...............................................................................................................................18
TRANSMISSION MEDIA INTERFACE ............................................................................................................................18
ARCNET CORE FUNCTIONAL DESCRIPTION .............................................................................................................24
MICROSEQUENCER .......................................................................................................................................................24
INTERNAL REGISTERS ..................................................................................................................................................24
INTERNAL RAM ...............................................................................................................................................................38
SOFTWARE INTERFACE................................................................................................................................................38
COMMAND CHAINING ....................................................................................................................................................42
RESET DETAILS ..............................................................................................................................................................45
INITIALIZATION SEQUENCE ..........................................................................................................................................45
IMPROVED DIAGNOSTICS.............................................................................................................................................46
COM20051 APPLICATIONS INFORMATION .................................................................................................................48
USING ARCNET DIAGNOSTICS TO OPTIMIZE YOUR SYSTEM................................................................................66
CABLING THE COM20051 ..............................................................................................................................................70
USING THE COM20051'S EMULATION MODE.............................................................................................................71
OPERATIONAL DESCRIPTION ......................................................................................................................................72
MAXIMUM GUARANTEED RATINGS.............................................................................................................................72
DC ELECTRICAL CHARACTERISTICS..........................................................................................................................72
TIMING DIAGRAMS .........................................................................................................................................................74
PACKAGE DIMENSIONS.................................................................................................................................................80
80 Arkay Drive
Hauppauge, NY 11788
(631) 435-6000
FAX (631) 273-3123
2
provides for an easy interface between the CPU
and the ARCNET core.
The networking core
is
based around an ARCNET Token Bus
protocol engine that provides highly-reliable and
fault tolerant message delivery at data rates
ranging from 5Mbps down to 156 Kbps with
message sizes varying from 1 to 508 bytes.
The
ARCNET protocol offers a simple,
standardized, and easily-understood networking
solution for any application.
The network
interface supports several media interfaces,
including RS-485, coaxial, and twisted pair in
either bus or star topologies.
The network
interface incorporates powerful diagnostic
features for network management and fault
isolation.
These include duplicate node ID
detection, reconfiguration detection, receive all
(monitor) mode, receiver activity, and token
detection.
PIN CONFIGURATION
VCC
P0.0/AD0
P0.1/AD1
6 5
P1.5
P1.6
P1.7
RST
P3.0/RXD
nPULSE1
P3.1/TXD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
7
8
9
10
11
12
13
14
15
16
17
4 3 2 1 44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
nEA/EMUL
TXEN
ALE
nPSEN
P2.7/A15
P2.6/A14
P2.5/A13
COM20051
18 19 20 21 22 23 24 25 26 27 28
XTAL2
XTAL1
VSS
P3.6/nWR
P3.7/nRD
nPULSE2
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
3
P0.2/AD2
P0.3/AD3
RXIN
P1.4
P1.3
P1.2
P1.1
P1.0
OVERVIEW
The COM20051 is essentially a network board-
in-a-chip. It takes an 80C32 microcontroller core
and an ARCNET controller and integrates them
into a single device. ARCNET is a token
passing-based protocol that combines powerful
flow control, error detection, and diagnostic
capabilities to deliver fast and reliable messages.
The COM20051 supports a variety of data rates
(5 Mbps to 156 Kbps), topologies (bus, star,
tree), and media types (RS-485, coax, twisted
pair, fiber optic, and powerline) to suit any type of
application.
The ARCNET network core of the COM20051
contains many features that make network
development simple and easy to comprehend.
Diagnostic features, such as Receive All,
Duplicate
ID
Detection,
Reconfiguration
Detection, Token, and Receiver Detection, all
combine to make the COM20051 simple to use
and to implement in any environment. The
ARCNET protocol itself is relatively simple to
understand and very flexible. A wide variety of
support products are available to assist in
network development, such as software drivers,
line drivers, boards, and development kits. The
COM20051 implements a full-featured 16MHz,
Intel-compatible 80C32 microcontroller with all of
the standard peripheral functions, including a full
duplex serial port, two timer/counters, one 8-bit
general purpose digital I/O port, and interrupt
controller. The 8051 architecture has long been
a standard in the embedded control industry for
low-level data acquisition and control. ARCNET
and the 8051 form a simple solution for many of
today's and tomorrow's low-level networking
solutions.
In addition to the 80C32 and the ARCNET
network core, the COM20051 contains all the
address decoding and interrupt routing logic to
interface the network core to the 80C32 core.
The integrated 8051/ARCNET combination
provides an extremely cost-effective and space-
efficient solution for industrial networking
applications. The COM20051 can be used in a
stand-alone embedded application, executing
control algorithms or performing data acquisition
and communicating data in a master/slave or
peer-to-peer
configuration, or used as a slave
processor handling communication tasks in a
multi-processing system.
DESCRIPTION OF PIN FUNCTIONS
PIN NO.
1
2-9
10
11
12
NAME
Receive In
P1.0-1.7
Reset
P3.0
nPulse 1
SYMBOL
RXIN
P1.0-1.7
RESET
P3.0
nPULSE1
DESCRIPTION
Input. Network receiver input.
Input/Output. Port 1 of the 8051. General purpose
digital I/O port.
Input. Active high reset.
Input/Output. Port 3 bit 0 of the 8051. RX input of
serial port.
Output. Network output. Open-drain when
backplane mode is invoked, otherwise it is a push-
pull output.
Input/Output. Port 3 bits 1-7 of the 8051.
Input. Oscillator inputs 1 and 2.
Ground pin.
13-19
20, 21
22
P3.1-3.7
P3.1-3.7
Crystal Oscillator XTAL1,
XTAL2
Ground
VSS
4
DESCRIPTION OF PIN FUNCTIONS
PIN NO.
NAME
23
nPulse 2
SYMBOL
nPULSE2
DESCRIPTION
Output. Network output. Outputs a synchronous
clock at 2x the data rate when backplane mode is
invoked.
Input/Output. Port 2 of the 8051. High order address
bus.
Output.
Output.
Output. This signal is used to enable the drivers for
transmitting. The polarity of this signal is
programmable by grounding the nPULSE2 pin prior
to the POWER-UP.
nPULSE2 floating prior to the power-up = TXEN
active high
nPULSE2 grounded prior to the power-up = TXEN
active low. (This option is available only in the
Backplane mode).
nEA
Input. When high, causes the 8051's outputs to tri-
state. When low, allows the 8051 to address external
memory. Must be low to execute code from the
embedded 8051.
Input/Output. Port 0 of the 8051. Multiplexed low
order address/data bus.
+5V power supply.
24-31
32
33
34
P2.0-2.7
P2.0-2.7
nProgram Store nPSEN
Enable
Address Latch
Enable
ALE
Transmit Enable TXEN
35
nEnable
36-43
44
P0.7-0.0
Power Supply
P0.7-0.0
VCC
RESET CIRCUIT FOR THE COM20051
The power on reset circuit for the COM20051 should be designed to provide a clean, fast transition time
TTL input to the COM20051. Sufficient signal high time on RST (pin 10) should be provided after Vcc
reaches +5V DC. The following circuit, which provides an 8ms power-on reset pulse, is recommended:
Vcc (+5V)
22uF/
10V
220
74LS14
RST (PIN 10)
5
FPGA/CPLD
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