CXD2951GA-2
Single Chip GPS LSI
Description
The CXD2951GA-2 is a dedicated single chip LSI
for the GPS (Global Positioning System), satellite-
based location measurement system. This LSI
enables the configuration of a single chip system
providing a cost-effective, low-power solution.
Compared with conventional methods, position
detection time and sensitivity are substantially
improved with the use of an advanced signal
processing scheme. With the integration of both the
Radio and baseband blocks into a single CMOS IC,
the CXD2951GA-2 is ideal for use in automotive,
cellular handset, handheld navigation, mobile
computing and other location-based applications.
Features
•
12-channel GPS receiver capable of simultaneously
receiving 12 satellites
•
Reception frequency: 1575.42MHz
(L1 band, CA code)
•
Reference clock (TCXO) frequency:
18.414MHz (GPS, Sony standard),
The unique frequency of major applications is available,
such as GSM and W-CDMA. (optional)
13.000MHz (GSM),
14.400MHz (CDMA),
16.368MHz (GPS),
19.800MHz (PDC/CDMA),
26.000MHz (GSM)
176 pin LFLGA (Plastic)
Radio
•
Image Rejection Mixer
•
VCO Tank
•
IF Filters
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings
•
Supply voltage I/O
IOV
DD
•
Supply voltage core
CV
DD
•
Supply voltage radio V
DD
•
Input voltage
V
I
•
Output voltage
V
O
•
Operating temperature Topr
•
Storage temperature Tstg
–0.5 to +4.6
–0.5 to +2.5
–0.5 to +2.5
–0.5 to +6
–0.5 to +6
–40 to +85
–50 to +150
V
V
V
V
V
°C
°C
•
32 bits RISC CPU (ARM7TDMI)
•
288K-bytes Program ROM
•
72K-bytes Data RAM
Power is supplied only to 8K-byte Data RAM while
in backup mode.
•
System power management
•
1-channel UART
•
Internal RTC (Real Time Clock)
•
10-bit successive approximation system A/D
converter, A/D data available on NMEA messages
•
All-in-view positioning
•
Communication format: Supports NMEA-0183
•
1 PPS output
•
Supports assisted-GPS for cellular (optional)
Recommended Operating Conditions
•
Supply voltage I/O
IOV
DD
3.0 to 3.6
V
∗
Under operation with internal ROM, using no
external expansion bus:
IOV
DD
2.6 to 3.6
V
∗
Under operation in backup mode:
BKUPIOV
DD
2.5 (Min.) V
•
Supply voltage core
CV
DD
1.62 to 1.98
V
•
Supply voltage radio V
DD
1.62 to 1.98
V
•
Operating temperature Topr
–40 to +85
°C
Input/Output Pin Capacitance (Baseband)
•
Input capacitance
C
IN
9 (Max.)
•
Output capacitance
C
OUT
11 (Max.)
•
I/O capacitance
C
I/O
11 (Max.)
pF
pF
pF
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E04445A49
CXD2951GA-2
Performance
Baseband
•
Tracking sensitivity:
–152dBm (average) or less
•
Acquisition sensitivity: –139dBm (average) or less in Normal mode
–150dBm (average) or less in High sensitivity mode
∗
Reference data using the Sony's reference board when using both an antenna of 0dBi and a RF amplifier
with NF
≤
2dB, 25dB gain.
•
TTFF (Time to First Fix):
Time until initial position measurement after power-on with the following conditions:
Cold Start (without both ephemeris and almanac time): 50s (average) / 60s (95% possibility)
Warm Start (without ephemeris but with almanac time): 35s (average) / 40s (95% possibility)
Hot Start (with both ephemeris and almanac time): 2s (minimum) / 6s (95% possibility)
∗
Reference data with elevation angle of 5° or more and no interception environment with satellite powers
≥
–130dBm. (Not in High sensitivity mode)
Note)
"95% possibility" means "position time with 95% possibility".
•
Positioning accuracy:
2DRMS: approx. 5m
∗
Reference data with elevation angle of 5° or more and no interception environment with satellite powers
≥
–130dBm.
•
Measurement data update time: 1s
•
Power consumption:
50mW (average) while position calculating with tracking satellites in low power mode
120mW (average) while position calculating with acquiring and tracking satellites
∗
Reference data using the Sony's reference board when the reference clock input is 18.414MHz, and its
amplitude is 3.3V swing.
•
1PPS output
1µs or less precision, 1PPS outputs from ECLKOUT (Pin 97).
Note)
These values are not guaranteed, depending on the conditions.
Radio
•
Total Gain (typ.):
100dB
•
Noise figure (typ.):
8dB
•
Synthesizer phase noise (typ.):
–70dBc/Hz (10kHz)
–80dBc/Hz (100kHz)
•
PLL spurious (typ.):
–45dBc (inside fosc ±1.023MHz)
–55dBc (outside fosc ±1.023MHz)
Note)
These values are not guaranteed.
–2–
CXD2951GA-2
System Block Diagram
1575.42MHz
TCXO
LNA
CPU
Freq.
Synthesizer
RF/IF
1575.42MHz
→
1.023MHz
BPF
SAW
TCXO
Reference clock
18.414MHz
(GPS, Sony standard)
LNA
Down
Converter
1.023MHz
LPF
1 bit
Acquisition Block
•
Acquire GPS signals
Tracking Block
•
Locking to GPS signals
•
12ch correlations
Costas Loop & DLL
Computation
& Control
•
Control Acquisition
& Tracking block
•
Position calculating
ARM7TDMI
I/O
UART
A/D
RTC
Timer
3ch
RAM
72KB
ROM
288KB
X'tal
32.768kHz
–3–
CXD2951GA-2
Pin Configuration
(Top View)
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
V
87
EA3
85
EA5
81
CV
SS
3
79
EA9
76
IOV
DD
2
75
IOV
SS
2
71
EA15
67
EA19
64
ETEST0
62
CV
SS
2
59
57
53
TEST
OUTP
50
49
47
RFIN
V
IF2GND IF1GND
MIXGND LNASRC
U
90
EA0
88
EA2
86
EA4
83
EA7
80
EA8
77
EA11
73
EA13
70
EA16
68
EA18
63
CV
DD
2
60
VCOM
56
IF1V
CC
54
48
46
45
44
42
U
TEST MIXGND MIXGND LNASRC MIXGND NRING
OUTN
T
92
CV
DD
4
89
EA1
84
EA6
82
CV
DD
3
78
EA10
74
EA12
72
EA14
69
EA17
66
65
61
RREF
58
52
55
51
40
43
41
T
ETEST2 ETEST1
IF2V
CC
TESTINN TEST TESTINP RFSUB RFRREF LNAMAT
OUTD
R
93
ECLKI
91
CV
SS
4
96
IOV
DD
3
37
39
38
R
V
DD
VCO VCODE V
SS
VCO
CAP
P
94
ECLKO
95
IOV
SS
3
98
EXROMI
33
V
DD
CP
35
LPFRF
36
V
SS
CP
P
N
102
97
100
31
32
34
LPFIF
N
EADVRB ECLKOUT EAVDPLL
V
DD
PLL V
SS
PLL
M
104
99
103
27
28
30
M
EVIN1 EAVSPLL EVIN0
ETESTTCK TMS RADIOSUB
L
106
101
105
EVIN2
29
24
26
TCK
L
EVIN3 EAVSAD
ETESTTMS TDI
K
110
108
107
25
21
22
K
ETEST3 EAVDAD EADVRT
ETESTTDI ETESTTINT TDO
J
112
IOV
DD
7
109
IOV
SS
8
111
ETEST4
23
ETESTTDO
19
CV
DD
1
18
CV
SS
1
J
H
115
114
113
20
TRST
15
17
H
ECCKI BKUPCV
DD
BKUPCV
SS
IOV
DD
1 EXTCXO
G
116
117
119
13
12
16
G
ECCKO BKUPIOV
SS
EOSCEN
EPORT12 EPORT11 ETCXO
F
118
121
122
11
9
14
F
BKUPIOV
DD
ECLKS1 ECLKS2
EPORT10 EPORT8 IOV
SS
1
E
120
123
125
EXCS1
7
EPORT6
6
10
E
ECLKS0 IOV
SS
4
EPORT5 EPORT9
D
126
EXOE
124
EXCS0
127
EXWE3
5
EPORT4
3
8
D
EPORT2 EPORT7
C
128
131
129
EXWE1
137
ED27
139
ED25
143
ED21
145
ED19
147
ED17
155
ED15
158
ED12
161
ED9
165
ED5
167
ED3
169
ED1
173
1
176
4
C
EXWE2 IOV
SS
5
ERXD0 EPORT0 IOV
DD
6 EPORT3
B
130
132
133
ED31
135
ED29
138
ED26
141
ED23
146
ED18
149
CV
SS
5
150
CV
DD
5
154
IOV
DD
5
157
ED13
159
ED11
163
ED7
164
ED6
171
CV
SS
6
175
IOV
SS
7
174
2
B
EXWE0 IOV
DD
4
ETXD0 EPORT1
A
134
ED30
136
ED28
140
ED24
142
ED22
144
ED20
148
ED16
151
152
153
156
160
ED10
162
ED8
166
ED4
168
ED2
170
ED0
172
CV
DD
6
A
EXRS ETESTXRS IOV
SS
6 ED14
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
: Pin 1 index.
–4–
CXD2951GA-2
Pin Description
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Symbol
EPORT0
EPORT1
EPORT2
EPORT3
EPORT4
EPORT5
EPORT6
EPORT7
EPORT8
EPORT9
EPORT10
EPORT11
EPORT12
IOV
SS
1
IOV
DD
1
ETCXO
EXTCXO
CV
SS
1
CV
DD
1
TRST
ETESTTINT
TDO
ETESTTDO
TDI
ETESTTDI
TCK
ETESTTCK
TMS
I
O
O
O
I
I
I
I
I
I
O
I/O
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Description
I/O port 0
(with a software controllable pull-down resistor, Connected to GND with a resistor.)
I/O port 1
(with a software controllable pull-down resistor, See software application note.)
I/O port 2
(with a software controllable pull-down resistor, See software application note.)
I/O port 3
(with a software controllable pull-down resistor, See software application note.)
I/O port 4
(with a software controllable pull-down resistor, See software application note.)
I/O port 5
(with a software controllable pull-down resistor, See software application note.)
I/O port 6
(with a software controllable pull-down resistor, See software application note.)
I/O port 7
(with a software controllable pull-down resistor, See software application note.)
I/O port 8
(with a software controllable pull-down resistor, See software application note.)
I/O port 9
(with a software controllable pull-down resistor, See software application note.)
I/O port 10
(with a software controllable pull-down resistor, See software application note.)
I/O port 11
(with a software controllable pull-down resistor, See software application note.)
I/O port 12
(with a software controllable pull-down resistor, See software application note.)
GND
3.3V
TCXO oscillator (Frequency selectable, See software application note.)
GND
1.8V
Test (Open, with a pull-down resistor)
Test
Test
Test
Test (Open, with a pull-up resistor)
Test (Open, with a pull-up resistor)
Test (Open, with a pull-down resistor)
Test (Open, with a pull-down resistor)
Test (Open, with a pull-up resistor)
–5–
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