Product Specification
PE4283
Product Description
The PE4283 RF Switch is designed to cover a broad range
of applications from DC through 4000 MHz. This reflective
switch integrates on-board CMOS control logic with a low
voltage CMOS-compatible control interface, and can be
controlled using either single-pin or complementary control
inputs. The PE4283 operates using a +3 volt power supply.
The PE4283 SPDT High Power RF Switch is manufactured
on Peregrine’s UltraCMOS™ process, a patented variation
of silicon-on-insulator (SOI) technology on a sapphire
substrate, offering the performance of GaAs with the
economy and integration of conventional CMOS.
Figure 1. Functional Diagram
RFC
SPDT High Power UltraCMOS™
DC – 4.0 GHz RF Switch
Features
•
Single-pin or complementary CMOS
logic control inputs
•
1.5 kV ESD tolerance
•
Low insertion loss: 0.65 dB at
1000 MHz, 0.70 dB at 2500 MHz
•
RFC-RF1/RF2 isolation of 33.5 dB at
1000 MHz, 21.5 dB at 2500 MHz
•
RF1-RF2 isolation of 37.5 dB at
•
Typical input 1 dB compression point
RF1
RF2
Operation Frequency
1
Insertion Loss
Isolation: RFC - RF1/RF2
Isolation: RF1 - RF2
Return Loss
‘ON’ Switching Time
‘OFF’ Switching Time
Input 1 dB Compression
Input IP3
N
Parameter
ot
Table 1. Electrical Specifications @ +25 °C, V
DD
= 3 V
(Z
S
= Z
L
= 50
Ω
)
Conditions
Min
DC
0.65
0.70
31.5
19.5
35.5
20
33.5
21.5
37.5
22
19
16
0.725
0.625
30
+32
+53
1.5
1.3
fo
V1
V2
rn
CMOS
Control
Driver
ew
Typical
de
s
ig
•
Ultra-small SC-70 package
Figure 2. Package Type SC-70
6-lead SC-70
ns
of +32 dBm
1000 MHz, 22 dB at 2500 MHz
Max
4000
0.75
0.80
Units
MHz
dB
dB
dB
dB
dB
dB
dB
dB
µs
µs
dBm
dBm
DC - 4000
1000 MHz
2500 MHz
1000 MHz
2500 MHz
1000 MHz
2500 MHz
1000 MHz
2500 MHz
50% CTRL to 0.1 dB of final value, 1 GHz
50% CTRL to 25 dB isolation, 1 GHz
1000 MHz
1000 MHz, 20 dBm input power
Note: 1. Device linearity will begin to degrade below 10 MHz.
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│
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©2005-2008 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 11
Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
PE4283
Product Specification
Figure 3. Pin Configuration (Top View)
pin 1
Table 4. Operating Ranges
Parameter
Min
2.0
Typ
3.0
Max
3.3
Units
V
RF1
GND
RF2
1
6
V2
RFC
V1
V
DD
Power Supply Voltage
I
DD
Power Supply Current
(V1 = 3V, V2 = 3V)
Control Voltage High
283
2
5
3
4
8
0.7x V
DD
50
µA
V
Table 2. Pin Descriptions
Pin
No.
1
2
3
4
5
Control Voltage Low
0.3x V
DD
V
Pin
Name
RF1
GND
RF2
V1
RFC
RF Port1
2
Description
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 3.
Switch control input, CMOS logic level.
RF Common
2
This pin supports two interface options:
Single-pin control mode.
A nominal 3-volt
supply connection is required.
Complementary-pin control mode.
A
complementary CMOS control signal
to V1 is supplied to this pin.
ew
V
6
V2
Note: 2. All RF pins must be DC blocked with an external series
capacitor or held at 0 VDC.
Symbol
V
DD
V
I
T
ST
T
OP
P
IN
Parameter/Conditions
Power supply voltage
Min
-0.3
fo
Table 3. Absolute Maximum Ratings
Max
4.0
Voltage on any DC input
Storage temperature
range
ot
-0.3
-65
-40
N
V
DD
+
0.3
150
85
+34
Operating temperature
range
Input power (50Ω)
ESD Voltage (HBM,
ML_STD 883 Method
3015.7)
ESD Voltage (MM,
JEDEC, JESD22-A114-B)
1500
100
V
ESD
rn
Units
V
V
°C
°C
dBm
V
Note: 3. Operating within DC limits (Table 4).
Document No. 70-0177-05
│
UltraCMOS™ RFIC Solutions
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be
restricted to the limits in the Operating Ranges
table. Operation between operating range
maximum and absolute maximum for extended
periods may reduce reliability.
©2005-2008 Peregrine Semiconductor Corp. All rights reserved.
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de
s
Figure 4. Maximum Operating Input Power
3
ig
RF Port2
2
ns
Ground connection. Traces should be
physically short and connected to ground
plane for best performance.
PE4283
Product Specification
Table 5. Single-pin Control Logic Truth Table
Control Voltages
Pin 6 (V2) = V
DD
Pin 4 (V1) = High
Pin 6 (V2) = V
DD
Pin 4 (V1) = Low
Control Logic Input
The PE4283 is a versatile RF CMOS switch that
supports two operating control modes; single-pin
control mode and complementary-pin control
mode.
Single-pin control mode
enables the switch to
operate with a single control pin (pin 4) supporting
a +3-volt CMOS logic input, and requires a
dedicated +3-volt power supply connection (pin 6).
This mode of operation reduces the number of
control lines required and simplifies the switch
control interface typically derived from a CMOS
µProcessor
I/O port.
Complementary-pin control mode
allows the
switch to operate using complementary control
pins V1 and V2 (pins 4 & 6), that can be directly
driven by +3-volt CMOS logic or a suitable
µProcessor
I/O port. This enables the PE4283 to
operate in positive control voltage mode within the
PE4283 operating limits.
Signal Path
RFC to RF1
RFC to RF2
Table 6. Complementary-pin Control Logic
Truth Table
Control Voltages
Pin 6 (V2 ) = Low
Pin 4 (V1) = High
Pin 6 (V2) = High
Pin 4 (V1) = Low
Signal Path
RFC to RF1
N
ot
fo
rn
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ig
RFC to RF2
ns
PE4283
Product Specification
Evaluation Kit
The SPDT switch EK Board was designed to ease
customer evaluation of Peregrine’s PE4283. The
RF common (RFC) port is connected through a
50
Ω
transmission line via the top SMA connector,
J1. RF1 and RF2 are connected through 50
Ω
transmission lines via SMA connectors J2 and J3,
respectively. A through 50
Ω
transmission is
available via SMA connectors J4 and J5. This
transmission line can be used to estimate the loss
of the PCB over the environmental conditions
being evaluated.
The board is constructed of a two metal layer FR4
material with a total thickness of 0.031”. The
bottom layer provides ground for the RF
transmission lines. The transmission lines were
designed using a coplanar waveguide with ground
plane model using a trace width of 0.0476”, trace
gaps of 0.030”, dielectric thickness of 0.028”,
metal thickness of 0.0021” and
ε
r
of 4.4.
J6 and J7 provide a means for controlling DC and
digital inputs to the device. J6-1 is connected to
the device V2 input. J7-1 is connected to the
device V1 input. Series resistors (R1 and R2) are
provided to reduce the package resonance
between RF and DC lines.
Figure 5. Evaluation Board Layouts
Peregrine Specification 101/0162
fo
rn
Figure 6. Evaluation Board Schematic
Peregrine Specification 102/0322
Document No. 70-0177-05
│
UltraCMOS™ RFIC Solutions
©2005-2008 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 11
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Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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ns
PE4283
Product Specification
Typical Performance Data
Figure 7. Insertion Loss @ 25 °C
Figure 8. Insertion Loss @ 3 V
Figure 9. Isolation: RF1-RF2 @ 25 °C
ew
N
ot
fo
rn
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Figure 10. Isolation: RF1-RF2 @ 3 V
ig
ns
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