Product Specification
PE4272
Product Description
The PE4272 RF Switch is designed for the TV tuner, PCTV, set
top box, DTV, DVR and general broadband applications. This
device offers industry leading broadband linearity, 1.5 kV ESD
tolerance and a simple CMOS interface. The device offers a
simple alternative solution to pin diode and mechanical relay
switches.
The PE4272 SPDT High Power RF Switch is manufactured on
Peregrine’s UltraCMOS™ process, a patented variation of
silicon-on-insulator (SOI) technology on a sapphire substrate,
offering the performance of GaAs with the economy and
integration of conventional CMOS.
Figure 1. Functional Diagram
RFC
SPDT Broadband UltraCMOS™
DC – 3 GHz RF Switch
Features
•
High ESD tolerance of 1.5 kV
•
Single-pin CMOS logic control
•
Low insertion loss: 0.5 dB at 1000 MHz,
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at 2000 MHz
+32 dBm
•
Small 8-lead MSOP package
0.6 dB at 2000 MHz
•
Isolation of 43 dB at 1000 MHz, 33.5 dB
•
Typical input 1 dB compression point of
Figure 2. Package Type
8-lead MSOP
RF1
RF2
CMOS
Control
Driver
V
DD
CTRL
Table 1. Electrical Specifications @ +25 °C, V
DD
= 3 V
(Z
S
= Z
L
= 75
Ω
)
Parameter
Conditions
Min
Typ
Max
Units
MHz
dB
Operation Frequency
1
DC – 3000
Insertion Loss
1000 MHz
2000 MHz
0.5
0.6
0.6
0.7
Isolation – RFC to RF1/RF2
1000 MHz
2000 MHz
1000 MHz
2000 MHz
41
31.5
41
32
43
33.5
43
34
dB
Isolation – RF1 to RF2
Return Loss
dB
1000 MHz
2000 MHz
19.5
16
500
dB
ns
‘ON’ Switching Time
3
50% CTRL to 0.1 dB final value, 2 GHz
50% CTRL to 25 dB isolation, 2 GHz
1000
‘OFF’ Switching Time
3
Video Feedthrough
2,3
500
<3
1000
ns
mV
pp
dBm
dBm
Input 1 dB Compression
3
1000 MHz
1000 MHz, 20 dBm input power
30
32
52
Input IP3
3
Notes:
1. Device linearity will begin to degrade below 5 MHz.
2. Measured with a 1 ns risetime, 0/3 V pulse and 500 MHz bandwidth.
3. Measured in a 50
Ω
system.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 11
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PE4272
Product Specification
Figure 3. Pin Configuration (Top View)
Table 4. Absolute Maximum Ratings
Symbol
V
DD
Parameter/Conditions
Power supply voltage
Voltage on any input
Storage temperature range
Input power (50
Ω)
ESD voltage (HBM, ML_STD
883 Method 3015.7)
Min
-0.3
-0.3
-65
Max
4.0
V
DD
+
0.3
150
34
1500
Units
V
V
°C
dBm
V
V
DD
CTRL
GND
1
2
8
7
RF1
V
I
GND
GND
RF2
4272
3
4
6
5
T
ST
P
IN
V
ESD
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RFC
Table 2. Pin Descriptions
Pin
No.
1
Pin
Name
V
DD
Description
Nominal +3 V supply connection.
CMOS logic level:
High = RFC to RF1 signal path
Low = RFC to RF2 signal path
2
CTRL
Absolute Maximum Ratings are those values
listed in the above table. Exceeding these values
may cause permanent device damage.
Functional operation should be restricted to the
limits in the Operating Ranges table. Exposure to
absolute maximum ratings for extended periods
may affect device reliability.
Latch-Up Avoidance
3
4
GND
RFC
RF2
Ground connection. Traces should be
physically short and connected to ground
plane for best performance.
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 4.
RF Common port.
4
RF2 port.
4
5
6
GND
7
8
GND
RF1
Ground Connection. Traces should be
physically short and connected to ground
plane for best performance.
Ground Connection. Traces should be
physically short and connected to ground
plane for best performance.
RF1 port.
4
Note:
4. All RF pins must be DC blocked with an external
series capacitor or held at 0 V
DC
.
Table 3. Operating Ranges
Parameter
Min
2.7
Typ
3.0
8
Max
3.3
20
Units
V
V
DD
Power Supply Voltage
I
DD
Power Supply Current
(V
DD
= 3 V, CTRL = 3 V)
Operating temperature
range
µA
°C
V
-40
85
Control Voltage High
0.7xV
DD
Control Voltage Low
0.3xV
DD
V
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 11
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UltraCMOS™ RFIC Solutions
PE4272
Product Specification
Table 5. Single-pin Control Logic Truth Table
Control Voltages
Pin 1 (V
DD
) = V
DD
Pin 2 (CTRL) = High
Pin 1 (V
DD
) = V
DD
Pin 2 (CTRL) = Low
Control Logic Input
The PE4272 is a versatile RF CMOS switch that
supports two operating control modes; single-pin
control mode and complementary-pin control
mode.
Single-pin control mode
enables the switch to
operate with a single control pin (pin 2) supporting
a +3-volt CMOS logic input, and requires a
dedicated +3-volt power supply connection (pin 1).
This mode of operation reduces the number of
control lines required and simplifies the switch
control interface typically derived from a CMOS
µProcessor
I/O port.
Signal Path
RFC to RF1
RFC to RF2
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Control Voltages
Signal Path
RFC to RF1
Pin 1 (V
DD
) = Low
Pin 2 (CTRL) = High
Pin 1 (V
DD
) = High
Pin 2 (CTRL) = Low
RFC to RF2
Table 6. Complementary-pin Control Logic
Truth Table
Complementary-pin control mode
allows the
switch to operate using complementary control
pins CTRL and V
DD
(pins 2 & 1), that can be
directly driven by +3-volt CMOS logic or a suitable
µProcessor
I/O port. This enables the PE4272 to
operate in positive control voltage mode within the
PE4272 operating limits.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 11
PE4272
Product Specification
Evaluation Kit
The SPDT Switch Evaluation Kit board was
designed to ease customer evaluation of the
PE4272 SPDT switch. The RF common port is
connected through a 75
Ω
transmission line to the
bottom F connector, J2. Port 1 and Port 2 are
connected through 75
Ω
transmission lines to two F
connectors on either side of the board, J1 and J3. A
through transmission line connects F connectors J4
and J5. This transmission line can be used to
estimate the loss of the PCB over the environmental
conditions being evaluated.
The board is constructed of a two metal layer FR4
material with a total thickness of 0.031”. The bottom
layer provides ground for the RF transmission lines.
The transmission lines were designed using a
coplanar waveguide with ground plane model using
a trace width of 0.021”, trace gaps of 0.030”,
dielectric thickness of 0.028”, copper thickness of
0.0021” and
ε
r
of 4.3.
Figure 4. Evaluation Board Layouts
Peregrine specification 101/0243
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J6 provides a means for controlling the DC inputs to
the device. The lower right pin (J6-2) is connected
to the device CTRL input. The upper right pin (J6-1)
is connected to the device V
DD
input. Footprints for
decoupling capacitors are provided on both CTRL
and V
DD
traces. It is the responsibility of the
customer to determine proper supply decoupling for
their design application. Removing these
components from the evaluation board has not been
shown to degrade RF performance.
Figure 5. Evaluation Board Schematic
Peregrine specification 102/0309
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 11
Document No. 70-0173-03
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UltraCMOS™ RFIC Solutions
PE4272
Product Specification
Typical Performance Data
Figure 6. Insertion Loss: RFC-RF1 @ 25 °C
Figure 7. Insertion Loss: RFC-RF1 @ 3 V
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Figure 8. Insertion Loss: RFC-RF2 @ 25 °C
Figure 9. Insertion Loss: RFC-RF2 @ 3 V
©2005 Peregrine Semiconductor Corp. All rights reserved.
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