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5962-9559510HXC

产品描述SRAM Module, 512KX8, 17ns, CMOS, CQFP68,
产品类别存储    存储   
文件大小187KB,共33页
制造商White Microelectronics
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5962-9559510HXC概述

SRAM Module, 512KX8, 17ns, CMOS, CQFP68,

5962-9559510HXC规格参数

参数名称属性值
Reach Compliance Codeunknown
最长访问时间17 ns
其他特性USER CONFIGURABLE AS 128K X 32
备用内存宽度16
JESD-30 代码S-CQFP-F68
JESD-609代码e4
长度39.6 mm
内存密度4194304 bit
内存集成电路类型SRAM MODULE
内存宽度8
功能数量1
端口数量1
端子数量68
字数524288 words
字数代码512000
工作模式ASYNCHRONOUS
最高工作温度125 °C
最低工作温度-55 °C
组织512KX8
输出特性3-STATE
可输出YES
封装主体材料CERAMIC, METAL-SEALED COFIRED
封装代码QFF
封装形状SQUARE
封装形式FLATPACK
并行/串行PARALLEL
认证状态Not Qualified
座面最大高度5.1 mm
最小待机电流2 V
最大供电电压 (Vsup)5.5 V
最小供电电压 (Vsup)4.5 V
标称供电电压 (Vsup)5 V
表面贴装YES
技术CMOS
温度等级MILITARY
端子面层GOLD
端子形式FLAT
端子节距1.27 mm
端子位置QUAD
宽度39.6 mm
Base Number Matches1

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REVISIONS
LTR
F
G
H
DESCRIPTION
Added device type 11. Added vendor CAGE code 0EU86 for device
types 05 through 09. -sld
Add note to paragraph 1.2.2 and table I, conditions. Add case
outline 9.
Correct figure 1, case outline M diagram, adding dimension "c", lead
thickness. Change figure 1, case outline M, A2 maximum dimension
from 0.015" to 0.025" and clarify A2 dimension in note 3.
Figure 1, case outline 9; changed the min limit for dimensions D2/E2
from 0.990 inches to 0.980 inches. Added vendor cage 88379 for the
case outline 9. Updated paragraph 1.2.3 to describe the five class
levels. -sld
Added device types 12 through 18. -sld
DATE (YR-MO-DA)
99-09-07
00-04-06
00-06-14
APPROVED
Raymond Monnin
Raymond Monnin
Raymond Monnin
J
01-05-06
Raymond Monnin
K
01-11-14
Raymond Monnin
REV
SHEET
REV
SHEET
REV STATUS
OF SHEETS
PMIC N/A
K
15
K
16
K
17
K
18
REV
SHEET
PREPARED BY
Steve L. Duncan
CHECKED BY
Michael C. Jones
K
19
K
20
K
21
K
1
K
22
K
2
K
23
K
3
K
24
K
4
K
25
K
5
K
26
K
6
K
7
K
8
K
9
K
10
K
11
K
12
K
13
K
14
STANDARD
MICROCIRCUIT
DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
POST OFFICE BOX 3990
COLUMBUS, OHIO 43216-5000
THIS DRAWING IS
AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
APPROVED BY
Kendall A. Cottongim
MICROCIRCUIT, HYBRID, MEMORY,
DIGITAL, STATIC RANDOM ACCESS
MEMORY, CMOS, 128K x 32-BIT
DRAWING APPROVAL DATE
95-07-19
REVISION LEVEL
K
SIZE
A
SHEET
CAGE CODE
67268
1 OF
26
5962-95595
DSCC FORM 2233
APR 97
DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.
5962-E622-01

 
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