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24AA00/24LC00/24C00

128 Bit I

2

C

™

Bus Serial EEPROM

Device Selection Table

Device

24AA00

24LC00

24C00

V

CC

Range

1.8 - 5.5

2.5 - 5.5

4.5 - 5.5

Temp Range

C,I

C,I,E

Package Types

8-PIN PDIP/SOIC

NC

Vss

1

8

V

CC

NC

SCL

SDA

24XX00

2

3

4

7

6

5

Features

• Low-power CMOS technology

- 500

µA

typical active current

- 250 nA typical standby current

• Organized as 16 bytes x 8 bits

• 2-wire serial interface bus, I

2

C™ compatible

• 100 kHz (1.8V) and 400 kHz (5V) compatibility

• Self-timed write cycle (including auto-erase)

• 4 ms maximum byte write cycle time

• 1,000,000 erase/write cycles

• ESD protection > 4 kV

• Data retention > 200 years

• 8L DIP, SOIC, TSSOP and 5L SOT-23 packages

• Standard or Pb-free finish available

• Temperature ranges available:

- Commercial (C):

0°C to +70°C

- Industrial (I):

-40°C to +85°C

- Automotive (E):

-40°C to +125°C

8-PIN TSSOP

NC

V

SS

1

2

3

4

8

7

6

5

V

CC

NC

SCL

SDA

24XX00

5-PIN SOT-23

SCL

V

SS

SDA

1

2

3

5

V

CC

24XX00

4

NC

Block Diagram

HV Generator

I/O

Control

Logic

Memory

Control

Logic

XDEC

EEPROM

Array

Description

The Microchip Technology Inc. 24AA00/24LC00/

24C00 (24XX00*) is a 128-bit Electrically Erasable

PROM memory organized as 16 x 8 with a 2-wire serial

interface. Low voltage design permits operation down

to 1.8 volts for the 24XX00 version, and every version

maintains a maximum standby current of only 1

µA

and

typical active current of only 500

µA.

This device was

designed for where a small amount of EEPROM is

needed for the storage of calibration values, ID

numbers or manufacturing information, etc. The

24XX00 is available in 8-pin PDIP, 8-pin SOIC (150

mil), 8-pin TSSOP and the 5-pin SOT-23 packages.

SDA

SCL

YDEC

V

CC

V

SS

Sense AMP

R/W Control

Pin Function Table

Name

V

SS

SDA

SCL

V

CC

Ground

Serial Data

Serial Clock

+1.8V to 5.5V (24AA00)

+2.5V to 5.5V (24LC00)

Function

I C is a trademark of Philips Corporation.

*24XX00 is used in this document as a generic part number for

the 24AA00/24LC00/24C00 devices.

NC

2

+4.5V to 5.5V (24C00)

No Internal Connection



2003 Microchip Technology Inc.

DS21178D-page 1

24AA00/24LC00/24C00

1.0

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

(†)

V

CC

.............................................................................................................................................................................6.5V

All inputs and outputs w.r.t. V

SS

......................................................................................................... -0.6V to V

CC

+1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied ................................................................................................-65°C to +125°C

ESD protection on all pins ..........................................................................................................................................4 kV

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional operation of the device at those or any other conditions

above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating

conditions for extended periods may affect device reliability.

TABLE 1-1:

DC CHARACTERISTICS

Commercial (C):

Industrial (I):

Automotive (E)

Symbol

V

IH

V

IL

V

HYS

V

OL

I

LI

I

LO

C

IN

,

C

OUT

I

CC

Write

I

CC

Read

I

CCS

—

.05 V

CC

T

A

= 0°C to +70°C,

T

A

= -40°C to +85°C,

T

A

= -40°C to +125°C,

Max.

Units

V

0.3 V

CC

—

0.4

±1

10

2

1

V

µA

pF

mA

µA

(Note)

V

CC

≥

2.5V

(Note)

I

OL

= 3.0 mA, V

CC

= 4.5V

I

OL

= 2.1 mA, V

CC

= 2.5V

V

IN

= V

CC

or V

SS

V

OUT

= V

CC

or V

SS

V

CC

= 5.0V

(Note)

T

A

= 25°C, f = 1 MHz

V

CC

= 5.5V, SCL = 400 kHz

V

CC

= 5.5V, SCL = 400 kHz

V

CC

= 5.5V, SDA = SCL = V

CC

V

CC

= 1.8V to 5.5V

V

CC

= 1.8V to 5.5V

V

CC

= 4.5V to 5.5V

Conditions

All Parameters apply across the

recommended operating ranges unless

otherwise noted

Parameter

SCL and SDA pins:

High-level input voltage

Low-level input voltage

Hysteresis of Schmitt Trigger

inputs

Low-level output voltage

Input leakage current

Output leakage current

Pin capacitance (all inputs/outputs)

Operating current

Standby current

Note:

Min.

0.7 V

CC

This parameter is periodically sampled and not 100% tested.

FIGURE 1-1:

BUS TIMING DATA

T

F

T

HIGH

T

R

SCL

T

SU

:

STA

T

LOW

T

HD

:

DAT

T

SU

:

DAT

T

SU

:

STO

SDA

IN

T

SP

T

HD

:

STA

T

BUF

T

AA

SDA

OUT

DS21178D-page 2



2003 Microchip Technology Inc.

24AA00/24LC00/24C00

TABLE 1-2:

AC CHARACTERISTICS

Commercial (C):

Industrial (I):

Automotive (E):

Symbol

F

CLK

Min

—

4000

600

4700

1300

—

4000

600

4700

600

0

250

100

4000

600

—

4700

1300

20+0.1

CB

—

1M

T

A

= 0°C to +70°C, V

CC

= 1.8V to 5.5V

T

A

= -40°C to +85°C, V

CC

= 1.8V to 5.5V

T

A

= -40°C to +125°C, V

CC

= 4.5V to 5.5V

Max

100

400

—

1000

300

—

3500

900

—

250

50

4

—

Units

kHz

Conditions

4.5V

≤

Vcc

≤

5.5V (E Temp range)

1.8V

≤

Vcc

≤

4.5V

≤

Vcc

≤

5.5V

4.5V

≤

Vcc

≤

5.5V (E Temp range)

1.8V

≤

Vcc

≤

4.5V

≤

Vcc

≤

5.5V

4.5V

≤

Vcc

≤

5.5V (E Temp range)

1.8V

≤

Vcc

≤

4.5V

≤

Vcc

≤

5.5V

4.5V

≤

Vcc

≤

5.5V (E Temp range)

1.8V

≤

Vcc

≤

4.5V

≤

Vcc

≤

5.5V

(Note 1)

4.5V

≤

Vcc

≤

5.5V (E Temp range)

1.8V

≤

Vcc

≤

4.5V

≤

Vcc

≤

5.5V

4.5V

≤

Vcc

≤

5.5V (E Temp range)

1.8V

≤

Vcc

≤

4.5V

≤

Vcc

≤

5.5V

(Note 2)

4.5V

≤

Vcc

≤

5.5V (E Temp range)

1.8V

≤

Vcc

≤

4.5V

≤

Vcc

≤

5.5V

4.5V

≤

Vcc

≤

5.5V (E Temp range)

1.8V

≤

Vcc

≤

4.5V

≤

Vcc

≤

5.5V

4.5V

≤

Vcc

≤

5.5V (E Temp range)

1.8V

≤

Vcc

≤

4.5V

≤

Vcc

≤

5.5V

4.5V

≤

Vcc

≤

5.5V (E Temp range)

1.8V

≤

Vcc

≤

4.5V

≤

Vcc

≤

5.5V

(Note 1),

CB

≤

100 pF

(Notes 1, 3)

All Parameters apply across all

recommended operating ranges

unless otherwise noted

Parameter

Clock frequency

Clock high time

T

HIGH

ns

Clock low time

T

LOW

ns

SDA and SCL rise time

(Note 1)

SDA and SCL fall time

Start condition hold time

T

R

ns

T

F

T

HD

:

STA

ns

Start condition setup time

T

SU

:

STA

ns

Data input hold time

Data input setup time

T

HD

:

DAT

T

SU

:

DAT

ns

Stop condition setup time

T

SU

:

STO

ns

Output valid from clock

(Note 2)

T

AA

ns

Bus free time: Time the bus must T

BUF

be free before a new transmis-

sion can start

Output fall time from V

IH

minimum to V

IL

maximum

Input filter spike suppression

(SDA and SCL pins)

Write cycle time

Endurance

Note 1:

2:

3:

4:

T

OF

T

SP

T

WC

ns

ms

cycles

(Note 4)

Not 100% tested. C

B

= total capacitance of one bus line in pF.

As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

The combined T

SP

and V

HYS

specifications are due to new Schmitt Trigger inputs which provide improved

noise spike suppression. This eliminates the need for a TI specification for standard operation.

This parameter is not tested but ensured by characterization. For endurance estimates in a specific

application, please consult the Total Endurance™ Model which can be obtained on www.microchip.com.



2003 Microchip Technology Inc.

DS21178D-page 3

24AA00/24LC00/24C00

2.0

2.1

PIN DESCRIPTIONS

SDA Serial Data

4.0

BUS CHARACTERISTICS

The following

bus protocol

has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is high. Changes in

the data line while the clock line is high will be

interpreted as a Start or Stop condition.

Accordingly, the following bus conditions have been

defined (Figure 4-1).

This is a bidirectional pin used to transfer addresses

and data into and data out of the device. It is an open

drain terminal, therefore the SDA bus requires a pull-up

resistor to V

CC

(typical 10 kΩ for 100 kHz, 2 kΩ for

400 kHz).

For normal data transfer SDA is allowed to change only

during SCL low. Changes during SCL high are

reserved for indicating the Start and Stop conditions.

2.2

SCL Serial Clock

4.1

Bus Not Busy (A)

This input is used to synchronize the data transfer from

and to the device.

Both data and clock lines remain high.

4.2

Start Data Transfer (B)

2.3

Noise Protection

The SCL and SDA inputs have Schmitt Trigger and

filter circuits which suppress noise spikes to assure

proper device operation even on a noisy bus.

A high-to-low transition of the SDA line while the clock

(SCL) is high determines a Start condition. All

commands must be preceded by a Start condition.

4.3

Stop Data Transfer (C)

3.0

FUNCTIONAL DESCRIPTION

The 24XX00 supports a bidirectional 2-wire bus and

data transmission protocol. A device that sends data

onto the bus is defined as a transmitter, and a device

receiving data as a receiver. The bus has to be

controlled by a master device which generates the

serial clock (SCL), controls the bus access, and

generates the Start and Stop conditions, while the

24XX00 works as slave. Both master and slave can

operate as transmitter or receiver, but the master

device determines which mode is activated.

A low-to-high transition of the SDA line while the clock

(SCL) is high determines a Stop condition. All

operations must be ended with a Stop condition.

4.4

Data Valid (D)

The state of the data line represents valid data when,

after a Start condition, the data line is stable for the

duration of the high period of the clock signal.

The data on the line must be changed during the low

period of the clock signal. There is one bit of data per

clock pulse.

Each data transfer is initiated with a Start condition and

terminated with a Stop condition. The number of the

data bytes transferred between the Start and Stop

conditions is determined by the master device and is

theoretically unlimited.

DS21178D-page 4



2003 Microchip Technology Inc.

24AA00/24LC00/24C00

4.5

Acknowledge

Each receiving device, when addressed, is obliged to

generate an acknowledge after the reception of each

byte. The master device must generate an extra clock

pulse which is associated with this Acknowledge bit.

Note:

The 24XX00 does not generate any

Acknowledge bits if an internal program-

ming cycle is in progress.

The device that acknowledges has to pull down the

SDA line during the Acknowledge clock pulse in such a

way that the SDA line is stable low during the high

period of the acknowledge related clock pulse. Of

course, setup and hold times must be taken into

account. A master must signal an end of data to the

slave by not generating an Acknowledge bit on the last

byte that has been clocked out of the slave. In this

case, the slave must leave the data line high to enable

the master to generate the Stop condition (Figure 4-2).

FIGURE 4-1:

SCL

(A)

(B)

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(C)

(D)

(C)

(A)

SDA

START

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

FIGURE 4-2:

ACKNOWLEDGE TIMING

Acknowledge

Bit

SCL

SDA

1

2

3

4

5

6

7

8

9

1

2

3

Data from transmitter

Receiver must release the SDA line at this point

so the Transmitter can continue sending data.

Transmitter must release the SDA line at this point

allowing the Receiver to pull the SDA line low to

acknowledge the previous eight bits of data.



2003 Microchip Technology Inc.

DS21178D-page 5

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