REVISIONS
LTR
A
DESCRIPTION
Add one vendor, CAGE 65786. Add device types 03 and 04. Add
margin test, programming procedure, waveform, and flowchart for
method B. Add case outline letter K.
Add "Changes in accordance with NOR 5962-R103-92."
Redraw with changes. Add device type 05 for vendor CAGE 65786.
Changes to margin methods A and B. Add vendor CAGE 66759 as a
source of supply for device types 01JX, 01LX, and 013X with vendor
similar part number changes. Editorial changes throughout.
Made correction to paragraph 1.2.2 for case outline 3, under package
style change rectangular to square. Updated drawing to the latest
format. Redrew entire document. -sld
Made correction to paragraph 1.2.1 and added additional vendor
similar PIN numbers for device types 03 and 05 on the Standard
Microcircuit Drawing Bulletin. -sld
Boilerplate update and part of five year review. tcr
DATE (YR MO DAY)
88-10-25
APPROVED
M. A. Frye
B
C
91-12-24
93-03-23
M. A. Frye
M. A. Frye
D
02-10-30
Raymond Monnin
E
02-12-16
Raymond Monnin
F
07-11-01
Robert M. Heber
THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED
REV
SHEET
REV
SHEET
REV STATUS
OF SHEETS
PMIC N/A
STANDARD
MICROCIRCUIT
DRAWING
THIS DRAWING IS
AVAILABLE
FOR USE BY All
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
REV
SHEET
PREPARED BY
Rick Officer
CHECKED BY
Charles Reusing
F
1
F
2
F
3
F
4
F
5
F
6
F
7
F
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F
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DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
http://www.dscc.dla.mil
APPROVED BY
Michael. A. Frye
MICROCIRCUIT, MEMORY, DIGITAL, CMOS,
2K x 8 UV ERASABLE PROM, MONOLITHIC
SILICON
DRAWING APPROVAL DATE
88-01-04
REVISION LEVEL
F
SIZE
A
SHEET
CAGE CODE
5962-87650
11
5962-E035-08
67268
1 OF
DSCC FORM 2233
APR 97
1. SCOPE
1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in
accordance with MIL-PRF-38535, appendix A.
1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example:
5962-87650
01
J
A
Drawing number
Device type
(see 1.2.1)
Case outline
(see 1.2.2)
Lead finish
(see 1.2.3)
1.2.1 Device type(s). The device type(s) identify the circuit function as follows:
Device type
01
02
03
04
05
Generic number
WS57C191-50, CY7C291-50
WS57C191-55
7C291-35, CY7C291-35, WS57C291C-35
WS57C191B-45
7C291A-25, WS57C291C-25
Circuit function
2K x 8 UV EPROM
2K x 8 UV EPROM
2K x 8 UV EPROM
2K x 8 UV EPROM
2K x 8 UV EPROM
Access time
50 ns
55 ns
35 ns
45 ns
25 ns
1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter
J
K
L
3
Descriptive designator
GDIP1-T24 or CDIP2-T24
GDFP2-F24 or CDFP3-F24
GDIP3-T24 or CDIP4-T24
CQCC1-N28
Terminals
24
24
24
28
Package style 1/
Dual-in-line
Flat package
Dual-in-line
Square leadless chip carrier
1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A.
1.3 Absolute maximum ratings.
Supply voltage range (V
CC
) ............................................................
Storage temperature range ...........................................................
Voltages on any pin with respect to ground ...................................
V
PP
with respect to ground ..............................................................
Power dissipation (P
D
) ....................................................................
Lead temperature (soldering, 10 seconds) ....................................
Thermal resistance, junction-to-case (θ
JC
) .....................................
Endurance .....................................................................................
Data retention ................................................................................
1.4 Recommended operating conditions.
Case operating temperature range (T
C
) ........................................
1/ Lid shall be transparent to permit ultraviolet light erasure.
2/ Must withstand the added P
D
due to short circuit test (e.g., I
OS
).
-55°C to +125°C
+4.5 V dc to +5.5 V dc
-65°C to +150°C
-0.6 V dc to +7.0 V dc
-0.6 V dc to +14.0 V dc
550 mW 2/
+300°C
See MIL-STD-1835
50 cycles/byte, minimum
10 years, minimum
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
A
REVISION LEVEL
5962-87650
SHEET
F
2
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a
part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in
the solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883 -
MIL-STD-1835 -
Test Method Standard Microcircuits.
Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 -
MIL-HDBK-780 -
List of Standard Microcircuit Drawings.
Standard Microcircuit Drawings.
(Copies of these documents are available online at
http://assist.daps.dla.mil/quicksearch/
or
http://assist.daps.dla.mil
or from
the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-
JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer
Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-
PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying
activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan
may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device.
These modifications shall not affect the PIN as described herein. A "Q" or "QML" certification mark in accordance with MIL-
PRF-38535 is required to identify when the QML flow option is used.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified
in MIL-PRF-38535, appendix A and herein.
3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.2 herein.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.
3.2.3 Truth table(s). See 3.2.3.1 and 3.2.3.2.
3.2.3.1 Unprogrammed or erased devices. The truth table for unprogrammed devices shall be as specified on figure 2.
3.2.3.2 Programmed devices. The requirements for supplying programmed devices are not part of this drawing.
3.2.4 Block diagram. The block diagram shall be as specified on figure 3.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
A
REVISION LEVEL
5962-87650
SHEET
F
3
3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are
as specified in table I and shall apply over the full case operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical
tests for each subgroup are described in table I.
3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed
in 1.2 herein. In addition, the manufacturer's PIN may also be marked. For packages where marking of the entire SMD PIN
number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device.
3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance
to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a "Q" or "QML" certification mark in
accordance with MIL-PRF-38535 to identify when the QML flow option is used.
3.6 Processing EPROMS. All testing requirements and quality assurance provisions herein shall be satisfied by the
manufacturer prior to delivery.
3.6.1 Erasure of EPROMS. When specified, devices shall be erased in accordance with the procedures and characteristics
specified in 4.4.
3.6.2 Programmability of EPROMS. When specified, devices shall be programmed to the specified pattern using the
procedures and characteristics specified in 4.5.
3.6.3 Verification of erasure or programmability of EPROMS. When specified, devices shall be verified as either
programmed to the specified pattern or erased. As a minimum, verification shall consist of performing a functional test
(subgroups 7 and 8) to verify that all bits are in proper state. Any bit that does not verify to be in the proper state shall
constitute a device failure and shall be removed from the lot.
3.7 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an
approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to
listing as an approved source of supply shall affirm that the manufacturer's product meets the requirements of MIL-PRF-38535,
appendix A and the requirements herein.
3.8 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided
with each lot of microcircuits delivered to this drawing.
3.9 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing
3.10 Verification and review. DSCC, DSCC's agent, and the acquiring activity retain the option to review the manufacturer's
facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the
reviewer.
3.11 Data retention. A data retention stress test shall be completed as part of the vendor's reliability monitors. This test shall
be done for initial characterization and after any design or process change which may affect data retention. The methods and
procedures may be vendor specific, but shall guarantee the number of years listed in section 1.3 herein over the full military
temperature range. The vendor's procedure shall be kept under document control and shall be made available upon request of
the acquiring or preparing activity, along with test data.
3.12 Endurance. A reprogrammability test shall be completed as part of the vendor's reliability monitors. This test shall be
done for initial characterization and after any design or process change which may affect the reprogrammability of the device.
The methods and procedures may be vendor specific, but shall guarantee the number of program/erase endurance cycles listed
in section 1.3 herein over the full military temperature range. The vendor's procedure shall be kept under document control and
shall be made available upon request of the acquiring or preparing activity, along with test data.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
A
REVISION LEVEL
5962-87650
SHEET
F
4
TABLE I. Electrical performance characteristics.
Test
Symbol
Conditions 1/
-55°C
≤
T
C
≤+125°C
4.5 V dc
≤
V
CC
≤
5.5 V dc
unless otherwise specified
V
CC
= 4.5 V and 5.5 V
V
CC
= 4.5 V and 5.5 V
I
OL
= 16 mA, V
CC
= 4.5 V,
V
IL
= 0.8 V, V
IH
= 2.0 V
I
OH
= -4 mA, V
CC
= 4.5 V,
V
IL
= 0.8 V, V
IH
= 2.0 V
V
CC
= 4.5 V and 5.5 V,
V
OUT
= GND
V
IN
= 5.5 V and GND
V
OUT
= 5.5 V and GND
CS
1
= V
IL
, V
CC
= 5.5 V,
O
0
to O
7
= 0 mA, CS2 = CS3 =
V
IH
, addresses cycling between
0 V and 3 V
CS
1
= V
IL
, V
CC
= 5.5 V,
O
0
to O
7
= 0 mA, CS2 = CS3 =
V
IH
V
IN
= 0, see 4.3.1c
V
OUT
= 0, see 4.3.1c
CS
1
= V
IL
, CS2 = CS3 = V
IH
,
See figures 4 and 5
Group A
subgroups
Device
types
Limits
Min
Max
Unit
Input low voltage
Input high voltage
Output low voltage 3/
Output high voltage 3/
Output short circuit
current
Input load current 4/
Output leakage
Operating current, TTL
inputs 5/ 6/ 7/
2/
V
IL
V
IH
V
OL
V
OH
I
OS
I
LI
I
LO
I
CC
TTL
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
All
All
All
All
All
All
All
All
-0.5
2/
2.0
0.8
V
CC
+0.5
2/
0.45
V
V
V
V
2.4
200
±10
±10
120
mA
μA
μA
mA
Operating current ,
CMOS inputs 2/ 7/ 8/
Input capacitance
Output capacitance
Address to output delay
I
CC
CMOS
C
IN
C
OUT
t
ACC
1,2,3
All
120
mA
4
4
9,10,11
All
All
01
02
03
04
05
10
12
50
55
35
45
25
25
30
20
25
20
0
pF
pF
ns
All chip selects to output
delay
t
CS
Either CS
1
, CS2 or CS3 9/
See figures 4 and 5
9,10,11
01,03,
04
02
05
ns
All chip selects high to
output float 2/
t
DF
Either CS
1
, CS2 or CS3 9/
See figures 4 and 5
9,10,11
01,02,
03,04
05
ns
Address to output hold
2/
t
OH
CS
1
= V
IL
, CS2 = CS3 = V
IH
,
See figures 4 and 5
9,10,11
All
ns
See footnotes at top of next page.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
A
REVISION LEVEL
5962-87650
SHEET
F
5
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