KC73125UCA
1/3 INCH CCD IMAGE SENSOR FOR NTSC CAMERA
INTRODUCTION
The KC73125UCA is an interline transfer CCD area image
sensor developed for NTSC 1/3 inch optical format video
cameras, surveillance cameras, object detectors and image
pattern recognizers. High sensitivity is achieved through the
adoption of Ye, Cy, Mg and G complementary color mosaic
filters, on-chip micro lenses and HAD (Hole Accumulated
Diode) photosensors. This chip features a field integration
read out system and an electronic shutter with variable charge
storage time.
16Pin Cer DIP
FEATURES
•
•
•
•
•
•
•
•
•
High Sensitivity
Optical Size 1/3 inch Format
Ye, Cy, Mg, G On-chip Comple-mentary Color
Mosaic Filter
Variable Speed Electronic Shutter
(1/60, 1/100 ~ 1/10,000sec)
Low Dark Current
Horizontal Register 5V Drive
16pin Ceramic DIP Package
Field Integration Read Out System
No DC Bias on Reset Gate
ORDERING INFORMATION
Device
KC73125UCA
Package
16Pin Cer DIP
Operating
-10
°C
~ +60
°C
STRUCTURE
•
•
•
•
•
Number of Total Pixels:
Number of Effective Pixels:
Chip Size:
Unit Pixel Size:
Optical Blacks & Dummies:
16 2
537(H)
×
505(V)
510(H)
×
492(V)
6.00mm(H)
×
4.95mm(V)
9.60µm(H)
×
7.50µm(V)
Refer to Figure Below
Vertical 1 Line (Even Field Only)
510
25
1
Dummy Pixels
Optical Black Pixels
Effective
Imaging
Area
OUTPUT
V-CCD
492
12
Effective Pixels
H-CCD
1
1/3 INCH CCD IMAGE SENSOR FOR NTSC CAMERA
KC73125UCA
BLOCK DIAGRAM
(Top View)
8
V
OUT
7
V
SS
6
V
GG
5
GND
Φ
V1
4
Φ
V2
3
Φ
V3
2
Φ
V4
1
Vertical Shift Register CCD
Vertical Shift Register CCD
Vertical Shift Register CCD
Vertical Shift Register CCD
Cy
Mg
Cy
Cy
G
Cy
Mg
Ye
G
Ye
Ye
Mg
Ye
G
Cy
Mg
Cy
Cy
G
Cy
Mg
Ye
G
Ye
Ye
Mg
Ye
G
Horizontal Shift Register CCD
9
V
DD
10
GND
11
SUB
12
V
L
Φ
RS
13
14
NC
Φ
H1
15
Φ
H2
16
Figure 1. Block Diagram
PIN DESCRIPTION
Table 1. Pin Description
Pin
1
2
3
4
5
6
7
8
Symbol
Φ
V4
Φ
V3
Φ
V2
Φ
V1
GND
V
GG
V
SS
V
OUT
Description
Vertical CCD transfer clock 4
Vertical CCD transfer clock 3
Vertical CCD transfer clock 2
Vertical CCD transfer clock 1
Ground
Output stage gate bias
Output stage source bias
Signal output
Pin
9
10
11
12
13
14
15
16
Symbol
V
DD
GND
SUB
V
L
Φ
RS
NC
Φ
H1
Φ
H2
Description
Output stage drain bias
Ground
Substrate bias
Protection circuit bias
Charge reset clock
No connection
Horizontal CCD transfer clock 1
Horizontal CCD transfer clock 2
2
KC73125UCA
1/3 INCH CCD IMAGE SENSOR FOR NTSC CAMERA
ABSOLUTE MAXIMUM RATINGS
(NOTE)
Table 2. Absolute Maximum Ratings
Characteristics
Substrate voltage
Supply voltage
SUB - GND
V
DD
, V
OUT
, V
SS
- GND
V
DD
, V
OUT
, V
SS
- SUB
Vertical clock input voltage
Φ
V1
,Φ
V2
,
Φ
V3
,
Φ
V4
- GND
Φ
V1
,
Φ
V2
,
Φ
V3
,
Φ
V4
- V
L
Φ
V1
,
Φ
V2
,
Φ
V3
,
Φ
V4
- SUB
Horizontal clock input voltage
Φ
H1
,
Φ
H2
- GND
Φ
H1
,
Φ
H2
- SUB
Voltage difference between vertical and
horizontal clock input pins
Φ
V1
,
Φ
V2
,
Φ
V3
,
Φ
V4
Symbols
Min.
-0.3
-0.3
-55
-10
-0.3
-55
-0.3
-55
Max.
55
18
10
20
30
10
10
17
15
27
Φ
H1
,
Φ
H2
Φ
H1
,
Φ
H2
-
Φ
V4
Output clock input voltage
Φ
RS
, V
GG
- GND
Φ
RS
, V
GG
- SUB
Protection circuit bias voltage
Operating temperature
Storage temperature
V
L
- SUB
T
OP
T
STG
-17
-0.3
-55
-55
-10
-30
17
17
15
10
10
60
80
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
°C
°C
NOTE:
The device can be destroyed, if the applied voltage or temperature is higher than the absolute maximum rating voltage
or temperature.
3
1/3 INCH CCD IMAGE SENSOR FOR NTSC CAMERA
KC73125UCA
DC CHARACTERISTICS
Table 3. DC Characteristics
Item
Output stage drain bias
Output stage gate voltage
Output stage source voltage
Substrate voltage adjustment range
Fluctuation voltage range after substrate
voltage adjusted
Protection circuit bias voltage
Output stage drain current
Symbol
V
DD
V
GG
V
SS
V
SUB
∆V
SUB
V
L
I
DD
Min.
14.55
1.75
Typ.
15.0
2.0
Max.
15.45
2.25
Unit
V
V
V
V
%
±5%
Remark
Ground through 680Ω
7.0
-3
14.5
3
The lowest vertical clock level
2.5
mA
CLOCK VOLTAGE CONDITIONS
Table 4. Clock Voltage Conditions
Item
Read-out clock voltage
Vertical transfer clock voltage
Symbol
V
VH1
, V
VH3
V
VM1
~ V
VM4
V
VL1
~ V
VL4
Horizontal transfer clock voltage
V
HH1
, V
HH2
V
HL1
, V
HL2
Charge reset clock voltage
V
RSH
V
RSL
Substrate clock voltage
V
ΦSUB
Min.
14.55
-0.2
-9.5
4.75
-0.2
4.75
-0.2
20
Typ.
15.0
0.0
-9.0
5.0
0.0
5.0
0.0
23.0
Max.
15.45
0.2
-8.5
5.25
0.2
5.25
0.2
25
Unit
V
V
V
V
V
V
V
V
Remark
High level
Middle
Low
High
Low
High
Low
Shutter
4
KC73125UCA
1/3 INCH CCD IMAGE SENSOR FOR NTSC CAMERA
DRIVE CLOCK WAVEFORM CONDITIONS
Read Out Clock Waveform
100%
90%
V
VH 1,
V
VH3
10%
0%
tr
twh
tf
0V
Vertical Transfer Clock Waveform
¥Õ
V 1
V
VH1
V
VH
V
VHH
V
VHL
¥Õ
V 3
V
VHH
V
V HL
V
VH L
V
VHL
V
VH3
V
VHH
V
VH H
V
VH
V
VL H
V
VL 1
V
VL L
V
VL 3
V
VL L
V
VL H
V
VL
V
VL
¥Õ
V 2
V
VH H
V
VHH
V
VH
V
VHL
¥Õ
V 4
V
VH
V
VH H
V
V HH
V
VH2
V
VHL
V
VHL
V
VH 4
V
VHL
V
VL 2
V
VL H
V
VL H
V
VL L
V
VL
V
VH
= ( V
V H 1
+ V
V H 2
)/ 2
V
VL 4
V
VL L
V
VL
V
VH H
= V
V H
+ 0. 3V
V
V L
= (V
V L 3
+ V
V L 4
)/ 2
V
¥Õ
V
= V
V H n
- V
V L n
(n =1~4)
V
V H L
= V
V H
- 0. 3 V
V
V L H
= V
V L
+ 0. 3V
V
V L L
= V
V L
- 0. 3 V
5
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