KC73133C
1/3 INCH CCD IMAGE SENSOR FOR VGA COMPATIBILITY
INTRODUCTION
The KC73133C is an interline transfer progressive scan type
square pixel CCD area image sensor of 1/3 inch optical
format developed for VGA. The electron accumulation time
can be changed by the electronic shutter function and it is
possible to obtain a frame still image without a mechanical
shutter. High resolution and good color reproduction are
accomplished by using mosaic R, G, B primary color filters. It
is suitable for still cameras and PC input cameras.
16Pin Cer DIP
FEATURES
•
•
•
•
•
•
•
•
•
•
•
330K Pixel Progressive-scan CCD
High Vertical Resolution (480 TV lines)
Square Unit Pixel for VGA Format
No Substrate Voltage Adjustment
No DC bias on Reset Clock
R, G, B Mosaic On-Chip Color Filter
Optical Size 1/3 inch Format
Variable Speed Electronic Shutter
Low Smear
High Antiblooming
Horizontal Register 5V Drive
ORDERING INFORMATION
Device
Package
Operating
KC73133C 16Pin Cer DIP 450mil -10
°C
~ +60
°C
STRUCTURE
•
•
•
•
•
Number of Total Pixels:
Number of Effective Pixels:
Chip Size:
Unit Pixel Size:
Optical Blacks & Dummies:
692(H)
×
504(V)
659(H)
×
494(V)
6.00mm(H)
×
4.95mm(V)
7.40µm(H)
×
7.40µm(V)
Refer to Figure Below
16 2
659
31
2
Dummy Pixels
Effective
Imaging
Area
(Top view)
OUTPUT
V-CCD
494
8
5
Optical Black Pixels
Effective Pixels
H-CCD
1
1/3 INCH CCD IMAGE SENSOR FOR VGA COMPATIBILITY
KC73133C
BLOCK DIAGRAM
(Top View)
8
V
OUT
7
GND
6
NC
5
GND
4
NC
Φ
V1
3
Φ
V2
2
Φ
V3
1
Vertical Shift Register CCD
Vertical Shift Register CCD
Vertical Shift Register CCD
Vertical Shift Register CCD
G
R
G
G
R
G
R
B
G
B
B
G
B
G
G
R
G
G
R
G
R
B
G
B
B
G
B
G
Horizontal Shift Register CCD
to substrate
9
V
DD
10
NC
11
GND
Φ
SUB
12
13
V
L
Φ
RS
14
Φ
H1
15
Φ
H2
16
Figure 1. Block Diagram
PIN DESCRIPTION
Table 1. Pin Description
Pin
1
2
3
4
5
6
7
8
Symbol
Φ
V3
Φ
V2
Φ
V1
NC
GND
NC
GND
V
OUT
Description
Vertical CCD transfer clock 3
Vertical CCD transfer clock 2
Vertical CCD transfer clock 1
No connection
Ground
No connection
Ground
Signal output
Pin
9
10
11
12
13
14
15
16
Symbol
V
DD
NC
GND
Φ
SUB
V
L
Φ
RS
Φ
H1
Φ
H2
Description
Output stage drain bias
No connection
Ground
Substrate clock
Protection circuit bias
Reset gate clock
Horizontal CCD transfer
Horizontal CCD transfer
2
KC73133C
1/3 INCH CCD IMAGE SENSOR FOR VGA COMPATIBILITY
ABSOLUTE MAXIMUM RATINGS
(1)
Table 2. Absolute Maximum Ratings
Characteristics
Substrate clock voltage
Symbols
Φ
SUB
- GND
Φ
SUB
- V
DD
Φ
SUB
- V
OUT
Supply voltage
Vertical clock input voltage
V
DD
, V
OUT
- GND
Φ
V1
- V
L
Φ
V2
,
Φ
V3
- V
L
Φ
V1
-
Φ
SUB
Φ
V2,
Φ
V3
-
Φ
SUB
Horizontal clock input voltage
Φ
H1
,
Φ
H2
- GND
Φ
H1
,
Φ
H2
- V
L
Φ
H1
,
Φ
H2
-
Φ
SUB
Output clock input voltage
Φ
RS
- V
L
Φ
RS
-
Φ
SUB
Φ
RS
- GND
Protection circuit bias voltage
Φ
SUB
- V
L
GND - V
L
Operating temperature
Storage temperature
T
OP
T
STG
Min.
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-40
-40
-0.3
-0.3
-40
-0.3
-40
-0.3
-16
-0.3
-10
-30
Max.
40
40
40
17
17
32
17
(2)
32
17
17
substrate DC bias
(3)
17
substrate DC bias
(2)
17
(2)
40
17
60
80
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
°C
°C
NOTE:
1. The device can be destroyed, if the applied voltage or temperature is higher than the absolute maximum rating voltage or
temperature.
2. V
DD
bias must be operated before reset pulse operation.
3. Substrate DC bias(OFD bias) must be operated before horizontal, reset pulse operation.
3
1/3 INCH CCD IMAGE SENSOR FOR VGA COMPATIBILITY
KC73133C
DC CHARACTERISTICS
Table 3. DC Characteristics
Item
Output stage drain bias
Protection circuit bias voltage
Substrate clock
Output stage drain current
Symbol
V
DD
V
L
Φ
SUB
I
DD
Min.
14.55
Typ.
15.0
Max.
15.45
Unit
V
Remark
The lowest vertical clock level
NOTE
V
mA
5.0
NOTE:
A DC bias (OFD bias) is generated within the CCD.
CLOCK VOLTAGE CONDITIONS
Table 4. Clock Voltage Conditions
Item
Read-out clock voltage
Vertical transfer clock voltage
Symbol
V
VH2
, V
VH3
V
VM1
~ V
VM3
V
VL1
~ V
VL3
Horizontal transfer clock voltage
V
HH1
, V
HH2
V
HL1
, V
HL2
Charge reset clock voltage
V
RSH
V
RSL
Substrate clock voltage
V
ΦSUB
Min.
14.55
-0.05
-8.0
4.75
-0.05
4.75
-0.05
21.5
Typ.
15.0
0.0
-7.5
5.0
0.0
5.0
0.0
22.5
Max.
15.45
0.05
-7.0
5.25
0.05
5.25
0.05
23.5
Unit
V
V
V
V
V
V
V
V
Remark
High
Middle
Low
High
Low
High
Low
Shutter
4
KC73133C
1/3 INCH CCD IMAGE SENSOR FOR VGA COMPATIBILITY
DRIVE CLOCK WAVEFORM CONDITIONS
Read Out Clock Waveform
100%
90%
V
VH 2,
V
VH3
10%
0%
tr
twh
tf
0V
Vertical Transfer Clock Waveform
¥Õ
V 1
V
V HH
V
VH L
V
V HL
V
VH3
V
VHH
V
VH
V
VL 3
V
VL L
V
VL H
V
VL
¥Õ
V 2
V
V HH
V
V HH
V
VH
V
VH L
¥Õ
V 3
V
VH
V
VH H
V
VHH
V
VH2
V
VH L
V
VHL
V
V H4
V
V HL
V
VL 2
V
VL H
V
VL H
V
VL L
V
VL
V
VH
= V
VH 2
V
VL 4
V
VL L
V
VL
V
VH H
= V
V H
+ 0. 3V
V
V L
= (V
V L 1
+ V
V L 3
)/ 2
V
¥Õ
V
= V
V H n
- V
V L n
(n =1~3 )
V
V H L
= V
V H
- 0. 3 V
V
V L H
= V
V L
+ 0. 3V
V
V L L
= V
V L
- 0. 3 V
5
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