KC74129C
1/4 INCH CCD IMAGE SENSOR FOR PAL CAMERA
INTRODUCTION
The KC74129C is an interline transfer CCD area image
sensor developed for PAL 1/4 inch optical format video
cameras, surveillance cameras, object detectors and image
pattern recognizers. High sensitivity is achieved through the
adoption of Ye, Cy, Mg and G complementary color mosaic
filters, on-chip micro lenses and HAD (Hole Accumulated
Diode) photosensors. This chip features a field integration
read out system and an electronic shutter with variable charge
storage time.
14Pin Cer DIP
FEATURES
•
•
•
•
•
•
•
•
•
•
High Sensitivity
Optical Size 1/4 inch Format
No Adjust Substrate Bias
Ye, Cy, Mg, G On-chip Complementary Color Mosaic Filter
Variable Speed Electronic Shutter
(1/60, 1/100 ~ 1/10,000sec)
Low Dark Current
Horizontal Register 3.3 to 5.0V Drive
14pin Ceramic DIP Package
Field Integration Read Out System
No DC Bias on Reset Gate
ORDERING INFORMATION
Device
KC74129C
Package
14Pin Cer DIP
Operating
-10
°C
~ +60
°C
STRUCTURE
•
•
•
•
•
Number of Total Pixels:
Number of Effective Pixels:
Chip Size:
Unit Pixel Size:
Optical Blacks & Dummies:
16 7
537(H)
×
597(V)
500(H)
×
582(V)
4.80mm(H)
×
4.04mm(V)
7.30µm(H)
×
4.70µm(V)
Refer to Figure Below
Vertical 1 Line (Even Field Only)
500
30
1
Dummy Pixels
Optical Black Pixels
Effective
Imaging
Area
OUTPUT
V-CCD
582
14
Effective Pixels
H-CCD
1
1/4 INCH CCD IMAGE SENSOR FOR PAL CAMERA
KC74129C
BLOCK DIAGRAM
(Top View)
7
V
OUT
6
GND
5
NC
Φ
V1
4
Φ
V2
3
Φ
V3
2
Φ
V4
1
Vertical Shift Register CCD
Vertical Shift Register CCD
Vertical Shift Register CCD
Vertical Shift Register CCD
Cy
Mg
Cy
Cy
G
Cy
Mg
Ye
G
Ye
Ye
Mg
Ye
G
Cy
Mg
Cy
Cy
G
Cy
Mg
Ye
G
Ye
Ye
Mg
Ye
G
Horizontal Shift Register CCD
8
V
DD
9
GND
Φ
SUB
10
11
V
L
Φ
RG
12
Φ
H1
13
Φ
H2
14
Figure 1. Block Diagram
PIN DESCRIPTION
Table 1. Pin Description
Pin
1
2
3
4
5
6
7
Symbol
Φ
V4
Φ
V3
Φ
V2
Φ
V1
NC
GND
V
OUT
Description
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
No connection
Ground
Signal output
Pin
8
9
10
11
12
13
14
Symbol
V
DD
GND
Φ
SUB
V
L
Φ
RG
Φ
H1
Φ
H2
Description
Signal output
GND
Substrate clock
Protection transistor bias
Reset gate clock
Horizontal register transfer clock
Horizontal register transfer clock
2
KC74129C
1/4 INCH CCD IMAGE SENSOR FOR PAL CAMERA
ABSOLUTE MAXIMUM RATINGS
(NOTE)
Table 2. Absolute Maximum Ratings
Characteristics
Substrate voltage
SUB - GND
V
DD
, V
OUT
- SUB
Vertical clock input voltage
Φ
V1
,
Φ
V3
, - GND
Φ
V2
,
Φ
V4
- GND
Φ
V1
,
Φ
V3
, - V
L
Φ
V2
,
Φ
V4
- V
L
Φ
V1
,
Φ
V2
,
Φ
V3
,
Φ
V4
- SUB
Horizontal clock input voltage
Φ
H1
,
Φ
H2
- V
L
Φ
H1
,
Φ
H2
- SUB
Voltage difference between vertical and
horizontal clock input pins
Φ
V1
,
Φ
V2
,
Φ
V3
,
Φ
V4
Φ
H1
,
Φ
H2
Φ
H1
,
Φ
H2
-
Φ
V4
Output clock input voltage
Φ
RG
- GND
Φ
RG
- SUB
Protection circuit bias voltage
Operating temperature
Storage temperature
V
L
- SUB
T
OP
T
STG
-17
-0.3
-40
-40
-10
-30
Symbols
Min.
-0.3
-40
-0.3
-0.3
-0.3
-0.3
-40
-0.3
-40
Max.
40
10
30
17
30
17
10
7
7
15
17
17
17
17
10
60
80
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
°C
°C
NOTE:
The device can be destroyed, if the applied voltage or temperature is higher than the absolute maximum rating voltage
or temperature.
3
1/4 INCH CCD IMAGE SENSOR FOR PAL CAMERA
KC74129C
DC CHARACTERISTICS
Table 3. DC Characteristics
Item
Output stage drain bias
Protection circuit bias voltage
Output stage drain current
Symbol
V
DD
V
L
I
DD
Min.
14.55
Typ.
15.0
Max.
15.45
Unit
V
The lowest vertical clock level
5
mA
CLOCK VOLTAGE CONDITIONS
Table 4. Clock Voltage Conditions
Item
Read-out clock voltage
Vertical transfer clock voltage
Symbol
V
VH1
, V
VH3
V
VM1
~ V
VM4
V
VL1
~ V
VL4
Horizontal transfer clock voltage
V
HH1
, V
HH2
V
HL1
, V
HL2
Charge reset clock voltage
V
RGH
V
RGL
Substrate clock voltage
V
ΦSUB
Min.
14.55
-0.2
-8.0
3.0
-0.05
4.75
-0.2
21.5
Typ.
15.0
0.0
-7.5
5.0
0.0
5.0
0.0
22.5
Max.
15.45
0.2
-7.0
5.25
0.05
5.25
0.2
23.5
Unit
V
V
V
V
V
V
V
V
Remark
High level
Middle
Low
High
Low
High
Low
Shutter
4
KC74129C
1/4 INCH CCD IMAGE SENSOR FOR PAL CAMERA
DRIVE CLOCK WAVEFORM CONDITIONS
Read Out Clock Waveform
100%
90%
V
VH 1,
V
VH3
10%
0%
tr
twh
tf
0V
Vertical Transfer Clock Waveform
¥Õ
V 1
V
VH1
V
VH
V
VHH
V
VHL
¥Õ
V 3
V
VHH
V
V HL
V
VH L
V
VHL
V
VH3
V
VHH
V
VH H
V
VH
V
VL H
V
VL 1
V
VL L
V
VL 3
V
VL L
V
VL H
V
VL
V
VL
¥Õ
V 2
V
VH H
V
VHH
V
VH
V
VHL
¥Õ
V 4
V
VH
V
VH H
V
V HH
V
VH2
V
VHL
V
VHL
V
VH 4
V
VHL
V
VL 2
V
VL H
V
VL H
V
VL L
V
VL
V
VH
= ( V
V H 1
+ V
V H 2
)/ 2
V
VL 4
V
VL L
V
VL
V
VH H
= V
V H
+ 0. 3V
V
V L
= (V
V L 3
+ V
V L 4
)/ 2
V
¥Õ
V
= V
V H n
- V
V L n
(n =1~4)
V
V H L
= V
V H
- 0. 3 V
V
V L H
= V
V L
+ 0. 3V
V
V L L
= V
V L
- 0. 3 V
5
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