DRAM MODULE
KMM5321204C2W/C2WG
KMM5321204C2W/C2WG Fast Page Mode with Extended Data Out
1M x 32 DRAM SIMM using 1Mx16 , 1K Refresh, 5V
GENERAL DESCRIPTION
The Samsung KMM5321204C2W is a 1Mx32bits Dynamic
RAM high density memory module. The Samsung
KMM5321204C2W consists of two CMOS 1Mx16bits DRAMs
in 42-pin SOJ package mounted on a 72-pin glass-epoxy sub-
strate. A 0.1 or 0.22uF decoupling capacitor is mounted on
the printed circuit board for each DRAM. The
KMM5321204C2W is a Single In-line Memory Module with
edge connections and is intended for mounting into 72 pin
edge connector sockets.
FEATURES
• Part Identification
- KMM5321204C2W(1024 cycles/16ms Ref, SOJ, Solder)
- KMM5321204C2WG(1024 cycles/16ms Ref, SOJ, Gold)
• Fast Page Mode with Extended Data Out
• CAS-before-RAS refresh capability
• RAS-only and hidden refresh capability
• TTL compatible inputs and outputs
• Single +5V
±10%
power supply
• JEDEC standard PDPin & pinout
• PCB : Height(750mil), single sided component
PERFORMANCE RANGE
Speed
-5
-6
t
RAC
50ns
60ns
t
CAC
15ns
17ns
t
RC
90ns
110ns
t
HPC
25ns
30ns
PIN CONFIGURATIONS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Symbol
V
SS
DQ0
DQ16
DQ1
DQ17
DQ2
DQ18
DQ3
DQ19
Vcc
NC
A0
A1
A2
A3
A4
A5
A6
Res(A10)
DQ4
DQ20
DQ5
DQ21
DQ6
DQ22
DQ7
DQ23
A7
Res(A11)
Vcc
A8
A9
Res(RAS1)
RAS0
NC
NC
Pin
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Symbol
NC
NC
Vss
CAS0
CAS2
CAS3
CAS1
RAS0
Res(RAS1)
NC
W
NC
DQ8
DQ24
DQ9
DQ25
DQ10
DQ26
DQ11
DQ27
DQ12
DQ28
Vcc
DQ29
DQ13
DQ30
DQ14
DQ31
DQ15
NC
PD1
PD2
PD3
PD4
NC
Vss
PIN NAMES
Pin Name
A0 - A9
DQ0 - DQ31
W
RAS0
CAS0 - CAS3
PD1 -PD4
Vcc
Vss
NC
Res
Function
Address Inputs
Data In/Out
Read/Write Enable
Row Address Strobe
Column Address Strobe
Presence Detect
Power(+5V)
Ground
No Connection
Reserved Pin
PRESENCE DETECT PINS (Optional)
Pin
PD1
PD2
PD3
PD4
50NS
Vss
Vss
Vss
Vss
60NS
Vss
Vss
NC
NC
* Pin connection changing available
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to
change products and specifications without notice.
-3-
Rev. 0.0 (Nov. 1997)
DRAM MODULE
ABSOLUTE MAXIMUM RATINGS *
Item
Voltage on any pin relative to V
SS
Voltage on V
CC
supply relative to V
SS
Storage Temperature
Power Dissipation
Short Circuit Output Current
Symbol
V
IN
, V
OUT
V
CC
T
stg
P
d
I
OS
KMM5321204C2W/C2WG
Rating
-1 to +7.0
-1 to +7.0
-55 to +150
2
50
Unit
V
V
°C
W
mA
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for in
tended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage referenced to V
SS
, T
A
= 0 to 70°C)
Item
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
*1 : V
CC
+2.0V/20ns, Pulse width is measured at V
CC
.
*2 : -2.0V/ 20ns, Pulse width is measured at V
SS
.
Symbol
V
CC
V
SS
V
IH
V
IL
Min
4.5
0
2.4
-1.0
*2
Typ
5.0
0
-
-
Max
5.5
0
V
CC+
1
*1
0.8
Unit
V
V
V
V
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)
Symbol
I
CC1
I
CC2
I
CC3
I
CC4
I
CC5
I
CC6
I
I(L)
I
O(L)
V
OH
V
OL
I
CC1
I
CC2
I
CC3
I
CC4
I
CC5
I
CC6
I
I(L)
I
O(L)
V
OH
V
OL
Speed
-5
-6
Don′t care
-5
-6
-5
-6
Don′t care
-5
-6
Don′t care
Don′t care
KMM5321204C2W/C2WG
Min
-
-
Max
300
280
4
300
280
240
220
2
300
280
10
5
-
0.4
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
uA
uA
V
V
-
-
-
-
-
-
-
-
-10
-5
2.4
-
: Operating Current * ( RAS, CAS, Address cycling @
t
RC
=min)
: Standby Current ( RAS=CAS=W=V
IH
)
: RAS Only Refresh Current * ( CAS=V
IH
, RAS cycling @
t
RC
=min)
: EDO Mode Current * ( RAS=V
IL
, CAS cycling :
t
HPC
=min)
: Standby Current ( RAS=CAS=W=Vcc-0.2V)
: CAS-Before-RAS Refresh Current * ( RAS and CAS cycling @
t
RC
=min)
: Input Leakage Current (Any input 0
≤V
IN
≤Vcc+0.5V,
all other pins not under test=0 V)
: Output Leakage Current(Data Out is disabled, 0V
≤V
OUT
≤Vcc)
: Output High Voltage Level (I
OH
= -5mA)
: Output Low Voltage Level (I
OL
= 4.2mA)
* NOTE
: I
CC1
, I
CC3
, I
CC4
and I
CC6
are dependent on output loading and cycle rates. Specified values are obtained with the output open.
I
CC
is specified as an average current. In I
CC1
and I
CC3
, address can be changed maximum once while RAS=V
IL
. In I
CC4
,
address can be changed maximum once within one EDO mode cycle,
t
HPC.
-5-
Rev. 0.0 (Nov. 1997)
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