DRAM MODULE
KMM53632000BK/BKG
KMM53632000BK/BKG Fast Page Mode
32M x 36 DRAM SIMM Using 16Mx4 & 16Mx1, 4K Refresh, 5V
GENERAL DESCRIPTION
The Samsung KMM53632000B is a 32Mx36bits Dynamic
RAM high density memory module. The Samsung
KMM53632000B consists of sixteen CMOS 16Mx4bits and
eight CMOS 16Mx1bit DRAMs in SOJ packages mounted on
a 72-pin glass-epoxy substrate. A 0.1 or 0.22uF decoupling
capacitor is mounted on the printed circuit board for each
DRAM. The KMM53632000B is a Single In-line Memory Mod-
ule with edge connections and is intended for mounting into
72 pin edge connector sockets.
FEATURES
• Part Identification
- KMM53632000BK(4K cycles/64ms Ref, SOJ, Solder)
- KMM53632000BKG(4K cycles/64ms Ref, SOJ, Gold)
• Fast Page Mode Operation
• CAS-before-RAS & Hidden Refresh capability
• RAS-only refresh capability
• TTL compatible inputs and outputs
• Single +5V±10% power supply
• JEDEC standard PDpin & pinout
• PCB : Height(1420mil), double sided component
PERFORMANCE RANGE
Speed
-5
-6
t
RAC
50ns
60ns
t
CAC
13ns
15ns
t
RC
90ns
110ns
t
PC
35ns
40ns
PIN CONFIGURATIONS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Symbol
V
SS
DQ0
DQ18
DQ1
DQ19
DQ2
DQ20
DQ3
DQ21
Vcc
NC
A0
A1
A2
A3
A4
A5
A6
A10
DQ4
DQ22
DQ5
DQ23
DQ6
DQ24
DQ7
DQ25
A7
A11
Vcc
A8
A9
RAS3
RAS2
DQ26
DQ8
Pin
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Symbol
DQ17
DQ35
Vss
CAS0
CAS2
CAS3
CAS1
RAS0
RAS1
NC
W
NC
DQ9
DQ27
DQ10
DQ28
DQ11
DQ29
DQ12
DQ30
DQ13
DQ31
Vcc
DQ32
DQ14
DQ33
DQ15
DQ34
DQ16
NC
PD1
PD2
PD3
PD4
NC
Vss
PIN NAMES
Pin Name
A0 - A11
DQ0 - 35
W
RAS0 - RAS3
CAS0 - CAS3
PD1 -PD4
Vcc
Vss
NC
Function
Address Inputs
Data In/Out
Read/Write Enable
Row Address Strobe
Column Address Strobe
Presence Detect
Power(+5V)
Ground
No Connection
PRESENCE DETECT PINS (Optional)
Pin
PD1
PD2
PD3
PD4
50NS
NC
Vss
Vss
Vss
60NS
NC
Vss
NC
NC
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to
change products and specifications without notice.
DRAM MODULE
FUNCTIONAL BLOCK DIAGRAM
DQ1
CAS
DQ2
U0
RAS
DQ3
OE W A0-A11 DQ4
DQ1
CAS
DQ2
U1
RAS
DQ3
OE W A0-A11 DQ4
U2
CAS
RAS W A0-A11
KMM53632000BK/BKG
DQ0~DQ3
CAS0
RAS0
DQ1
DQ2
DQ3
DQ4
DQ1
DQ2
DQ3
DQ4
D
Q
DQ1
DQ2
DQ3
DQ4
DQ1
DQ2
DQ3
DQ4
D
Q
DQ1
DQ2
DQ3
DQ4
DQ1
DQ2
DQ3
DQ4
D
Q
DQ1
DQ2
DQ3
DQ4
DQ1
DQ2
DQ3
DQ4
D
Q
CAS
RAS
W A0-A11 OE
U12
CAS0
RAS1
DQ4~DQ7
CAS
RAS
W A0-A11 OE
U13
D
Q
DQ8
DQ9~DQ12
CAS
W A0-A11 RAS
CAS
RAS
W A0-A11 OE
U15
U14
CAS1
DQ1
CAS
DQ2
U3
RAS
DQ3
OE W A0-A11 DQ4
DQ1
CAS
DQ2
U4
RAS
DQ3
OE W A0-A11 DQ4
U5
CAS
RAS W A0-A11
CAS1
DQ13~DQ16
CAS
RAS
W A0-A11 OE
U16
D
Q
DQ17
CAS
W A0-A11 RAS
CAS
RAS
W A0-A11 OE
U18
U17
CAS2
RAS2
DQ1
CAS
DQ2
U6
RAS
DQ3
OE W A0-A11 DQ4
DQ1
CAS
DQ2
U7
RAS
DQ3
OE W A0-A11 DQ4
U8
CAS
RAS W A0-A11
DQ18~DQ21
CAS2
RAS3
DQ22~DQ25
CAS
RAS
W A0-A11 OE
U19
D
Q
DQ26
DQ27~DQ30
CAS
W A0-A11 RAS
CAS
RAS
W A0-A11 OE
U21
U20
CAS3
DQ1
CAS
DQ2
U9
RAS
DQ3
OE W A0-A11 DQ4
DQ1
CAS
DQ2
U10
RAS
DQ3
OE W A0-A11 DQ4
U11
CAS
RAS W A0-A11
CAS3
DQ31~DQ34
CAS
RAS
W A0-A11 OE
U22
D
Q
DQ35
CAS
W A0-A11 RAS
U23
W
A0-A11
Vcc
0.1 or 0.22uF Capacitor
for each DRAM
Vss
To all DRAMs
DRAM MODULE
ABSOLUTE MAXIMUM RATINGS *
Item
Voltage on any pin relative to V
SS
Voltage on V
CC
supply relative to V
SS
Storage Temperature
Power Dissipation
Short Circuit Output Current
Symbol
V
IN
, V
OUT
V
CC
T
stg
P
d
I
OS
KMM53632000BK/BKG
Rating
-1 to +7.0
-1 to +7.0
-55 to +125
24
50
Unit
V
V
°C
W
mA
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage referenced to V
SS
, T
A
= 0 to 70°C)
Item
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min
4.5
0
2.4
-1.0
*2
Typ
5.0
0
-
-
Max
5.5
0
V
CC*1
0.8
Unit
V
V
V
V
*1 : V
CC
+2.0V at pulse width≤20ns, which is measured at V
CC
.
*2 : -2.0V at pulse width≤20ns, which is measured at V
SS
.
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)
Symbol
I
CC1
I
CC2
I
CC3
I
CC4
I
CC5
I
CC6
I
I(L)
I
O(L)
V
OH
V
OL
Speed
-5
-6
Don′t care
-5
-6
-5
-6
Don′t care
-5
-6
Don′t care
Don′t care
KMM53632000BK/BKG
Min
-
-
Max
1344
1224
48
1344
1224
904
784
24
1344
1224
10
10
-
0.4
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
uA
uA
V
V
-
-
-
-
-
-
-
-
-10
-10
2.4
-
I
CC1
: Operating Current * (RAS, CAS, Address cycling @
t
RC
=min)
I
CC2
: Standby Current (RAS=CAS=W=V
IH
)
I
CC3
: RAS Only Refresh Current * (CAS=V
IH
, RAS cycling @
t
RC
=min)
I
CC4
: Fast Page Mode Current * (RAS=V
IL
, CAS cycling :
t
PC
=min)
I
CC5
: Standby Current (RAS=CAS=W=Vcc-0.2V)
I
CC6
: CAS-Before-RAS Refresh Current * (RAS and CAS cycling @
t
RC
=min)
I(
IL)
: Input Leakage Current (Any input 0≤V
IN
≤Vcc+0.5V,
all other pins not under test=0 V)
I(
OL)
: Output Leakage Current(Data Out is disabled, 0V≤V
OUT
≤Vcc)
V
OH
: Output High Voltage Level (I
OH
= -5mA)
V
OL
: Output Low Voltage Level (I
OL
= 4.2mA)
* NOTE
: I
CC1
, I
CC3
, I
CC4
and I
CC6
are dependent on output loading and cycle rates. Specified values are obtained with the output open.
I
CC
is specified as an average current. In I
CC1
and I
CC3
, address can be changed maximum once while RAS=V
IL
. In I
CC4
,
address can be changed maximum once within one Fast page mode cycle time,
t
PC.
DRAM MODULE
CAPACITANCE
(T
A
= 25°C, V
CC
=5V, f = 1MHz)
Item
Input capacitance[A0-A11]
Input capacitance[W]
Input capacitance[RAS0 - RAS3]
Input capacitance[CAS0 - CAS3]
Input/Output capacitance[DQ0-35]
Symbol
C
IN1
C
IN2
C
IN3
C
IN4
C
DQ
Min
-
-
-
-
-
KMM53632000BK/BKG
Max
130
178
52
52
17
Unit
pF
pF
pF
pF
pF
AC CHARACTERISTICS
(0°C≤T
A
≤70°C,
V
CC
=5.0V±10%. See notes 1,2.)
Test condition : V
ih
/V
il
=2.4/0.8V, V
oh
/V
ol
=2.4/0.4V, output loading CL=100pF
Parameter
Random read or write cycle time
Access time from RAS
Access time from CAS
Access time from column address
CAS to output in Low-Z
Output buffer turn-off delay
Transition time(rise and fall)
RAS precharge time
RAS pulse width
RAS hold time
CAS hold time
CAS pulse width
RAS to CAS delay time
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold referenced to CAS
Read command hold referenced to RAS
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data set-up time
Data hold time
Refresh period
Write command set-up time
CAS setup time(CAS-before-RAS refresh)
CAS hold time(CAS-before-RAS refresh)
RAS to CAS precharge time
Access time from CAS precharge
Symbol
-5
Min
90
50
13
25
0
0
1
30
50
13
50
13
20
15
5
0
10
0
10
25
0
0
0
10
10
15
13
0
10
64
0
5
10
5
30
0
5
10
5
35
10K
37
25
10K
13
50
0
0
1
40
60
15
60
15
20
15
5
0
10
0
10
30
0
0
0
10
10
15
15
0
10
64
10K
45
30
10K
15
50
Max
Min
110
60
15
30
-6
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
3
7
9
9
8
8
4
10
3,4,10
3,4,5
3,10
3
6
2
Note
t
RC
t
RAC
t
CAC
t
AA
t
CLZ
t
OFF
t
T
t
RP
t
RAS
t
RSH
t
CSH
t
CAS
t
RCD
t
RAD
t
CRP
t
ASR
t
RAH
t
ASC
t
CAH
t
RAL
t
RCS
t
RCH
t
RRH
t
WCH
t
WP
t
RWL
t
CWL
t
DS
t
DH
t
REF
t
WCS
t
CSR
t
CHR
t
RPC
t
CPA
DRAM MODULE
AC CHARACTERISTICS
(0°C≤T
A
≤70°C,
V
CC
=5.0V±10%. See notes 1,2.)
Test condition : V
ih
/V
il
=2.4/0.8V, V
oh
/V
ol
=2.4/0.4V, output loading CL=100pF
Parameter
Fast page mode cycle time
CAS precharge time(Fast page cycle)
RAS pulse width(Fast page cycle)
W to RAS precharge time(C-B-R refresh)
W to RAS hold time(C-B-R refresh)
Symbol
-5
Min
35
10
50
10
10
200K
Max
KMM53632000BK/BKG
-6
Min
40
10
60
10
10
200K
Max
Unit
ns
ns
ns
ns
ns
Note
t
PC
t
CP
t
RASP
t
WRP
t
WRH
NOTES
1. An initial pause of 200us is required after power-up followed
by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
2. Input voltage levels are V
ih
/V
il
. V
IH
(min) and V
IL
(max) are ref-
erence levels for measuring timing of input signals. Transi-
tion times are measured between V
IH
(min) and V
IL
(max) and
are assumed to be 5ns for all inputs.
3. Measured with a load equivalent to 2 TTL loads and 100pF.
8. Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
4. Operation within the
t
RCD
(max) limit insures that
t
RAC
(max)
can be met.
t
RCD
(max) is specified as a reference point only.
If
t
RCD
is greater than the specified
t
RCD
(max) limit, then
access time is controlled exclusively by
t
CAC
.
5. Assumes that
t
RCD
≥
t
RCD
(max).
9. These parameters are referenced to the CAS leading edge in
early write cycles.
10. Operation within the
t
RAD
(max) limit insures that
t
RAC
(max)
can be met.
t
RAD
(max) is specified as reference point only. If
t
RAD
is greater than the specified
t
RAD
(max) limit, then
access time is controlled by
t
AA
.
6. This parameter defines the time at which the output achieves
the open circuit condition and is not referenced to V
OH
or
V
OL
.
7.
t
WCS
is non-restrictive operating parameter. It is included in
the data sheet as electrical characteristics only. If
t
WCS
≥
t
WCS
(min), the cycle is an early write cycle and the
data out pin will remain high impedance for the duration of
the cycle.
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