DRAM MODULE
KMM5364003CK/CKG
KMM5364103CK/CKG
4Byte 4Mx36 SIMM
(4Mx4 & 16M Quad CAS base)
Revision 0.1
Nov. 1997
DRAM MODULE
Revision History
Version 0.1 (Nov. 1997)
• Changed the mode of parity check component from EDO to FP, refer to
KMM5364003CK/CKG
KMM5364103CK/CKG
PACKAGE DIMENSIONS
and
GENERAL DISCRIPTION.
DRAM MODULE
KMM5364003CK/CKG
KMM5364103CK/CKG
KMM5364003CK/CKG & KMM5364103CK/CKG with Fast Page Mode
4M x 36 DRAM SIMM using 4Mx4 and 16M Quad CAS, 4K/2K Refresh, 5V
GENERAL DESCRIPTION
The Samsung KMM53640(1)03CK is a 4Mx36bits Dynamic
RAM high density memory module. The Samsung
KMM53640(1)03CK consists of eight CMOS 4Mx4bits DRAMs
in 24-pin SOJ package and one CMOS 4Mx4 bit Quad CAS
DRAM in 28-pin SOJ package mounted on a 72-pin glass-
epoxy substrate. A 0.1 or 0.22uF decoupling capacitor is
mounted on the printed circuit board for each DRAM. The
KMM53640(1)03CK is a Single In-line Memory Module with
edge connections and is intended for mounting into 72 pin
edge connector sockets.
FEATURES
• Part Identification
- KMM5364003CK(4096 cycles/64ms Ref, SOJ, Solder)
- KMM5364003CKG(4096 cycles/64ms Ref, SOJ, Gold)
- KMM5364103CK(2048 cycles/32ms Ref, SOJ, Solder)
- KMM5364103CKG(2048 cycles/32ms Ref, SOJ, Gold)
• Fast Page Mode Operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• TTL compatible inputs and outputs
• Single +5V
±10%
power supply
• JEDEC standard PDPin & pinout
• PCB : Height(1000mil), single sided component
PERFORMANCE RANGE
Speed
-5
-6
t
RAC
50ns
60ns
t
CAC
13ns
15ns
t
RC
90ns
110ns
PIN CONFIGURATIONS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Symbol
V
SS
DQ0
DQ18
DQ1
DQ19
DQ2
DQ20
DQ3
DQ21
Vcc
NC
A0
A1
A2
A3
A4
A5
A6
A10
DQ4
DQ22
DQ5
DQ23
DQ6
DQ24
DQ7
DQ25
A7
A11
Vcc
A8
A9
Res(RAS1)
RAS0
DQ26
DQ8
Pin
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Symbol
DQ17
DQ35
Vss
CAS0
CAS2
CAS3
CAS1
RAS0
Res(RAS1)
NC
W
NC
DQ9
DQ27
DQ10
DQ28
DQ11
DQ29
DQ12
DQ30
DQ13
DQ31
Vcc
DQ32
DQ14
DQ33
DQ15
DQ34
DQ16
NC
PD1
PD2
PD3
PD4
NC
Vss
PIN NAMES
Pin Name
A0 - A11
A0 - A10
DQ0 - DQ35
W
RAS0
CAS0 - CAS3
PD1 -PD4
Vcc
Vss
NC
Function
Address Inputs(4K Ref)
Address Inputs(2K Ref)
Data In/Out
Read/Write Enable
Row Address Strobe
Column Address Strobe
Presence Detect
Power(+5V)
Ground
No Connection
PRESENCE DETECT PINS (Optional)
Pin
PD1
PD2
PD3
PD4
50NS
Vss
NC
Vss
Vss
60NS
Vss
NC
NC
NC
* Pin connection changing available
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to
change products and specifications without notice.
* NOTE : A11 is used for only KMM5364003CK/CKG (4K ref.)
DRAM MODULE
FUNCTIONAL BLOCK DIAGRAM
CAS0
RAS0
CAS
RAS
OE
DQ0
DQ1
U0
DQ2
A0-
A11(A10) DQ3
DQ0
DQ1
U1
DQ2
A0-
A11(A10) DQ3
DQ0
DQ1
DQ2
A0-
A11(A10) DQ3
DQ0
DQ1
DQ2
A0-
A11(A10) DQ3
KMM5364003CK/CKG
KMM5364103CK/CKG
DQ0-DQ3
W
CAS
RAS
OE
DQ4-DQ7
W
CAS1
CAS
RAS
OE
U2
W
DQ9-DQ12
CAS
RAS
OE
U3
W
DQ13-DQ16
CAS2
CAS
RAS
OE
W
DQ0
U4
DQ1
DQ2
A0-
A11(A10) DQ3
DQ0
DQ1
DQ2
A0-
A11(A10) DQ3
DQ0
DQ1
DQ2
A0-
A11(A10) DQ3
DQ0
DQ1
DQ2
A0-
A11(A10) DQ3
DQ18-DQ21
CAS
RAS
OE
U5
W
DQ22-DQ25
CAS3
CAS
RAS
OE
U6
W
DQ27-DQ30
CAS
RAS
OE
U7
W
DQ31-DQ34
CAS0
CAS1
CAS2
CAS3
RAS
OE W
W
A0-A11(A10)
Vcc
U8
DQ0
DQ1
DQ2
DQ3
DQ8
DQ17
DQ26
DQ35
A0-
A11(A10)
.1 or .22uF Capacitor
for each DRAM
Vss
To all DRAMs
DRAM MODULE
ABSOLUTE MAXIMUM RATINGS *
Item
Voltage on any pin relative to V
SS
Voltage on V
CC
supply relative to V
SS
Storage Temperature
Power Dissipation
Short Circuit Output Current
Symbol
V
IN
, V
OUT
V
CC
T
stg
P
d
I
OS
KMM5364003CK/CKG
KMM5364103CK/CKG
Rating
-1 to +7.0
-1 to +7.0
-55 to +150
9
50
Unit
V
V
°C
W
mA
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for in
tended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage referenced to V
SS
, T
A
= 0 to 70°C)
Item
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
*1 : V
CC
+2.0V/20ns, Pulse width is measured at V
CC
.
*2 : -2.0V/ 20ns, Pulse width is measured at V
SS
.
Symbol
V
CC
V
SS
V
IH
V
IL
Min
4.5
0
2.4
-1.0
*2
Typ
5.0
0
-
-
Max
5.5
0
V
CC
+1
*1
0.8
Unit
V
V
V
V
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)
Symbol
I
CC1
I
CC2
I
CC3
I
CC4
I
CC5
I
CC6
I
I(L)
I
O(L)
V
OH
V
OL
I
CC1
I
CC2
I
CC3
I
CC4
I
CC5
I
CC6
I
I(L)
I
O(L)
V
OH
V
OL
Speed
-5
-6
Don′t care
-5
-6
-5
-6
Don′t care
-5
-6
Don′t care
Don′t care
KMM5364003CK/CKG
Min
-
-
KMM5364103CK/CKG
Min
-
-
Max
810
720
18
810
720
720
630
9
810
720
45
5
-
0.4
Max
990
900
18
990
900
810
720
9
990
900
45
5
-
0.4
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
uA
uA
V
V
-
-
-
-
-
-
-
-
-45
-5
2.4
-
-
-
-
-
-
-
-
-
-45
-5
2.4
-
: Operating Current * ( RAS, CAS, Address cycling @
t
RC
=min)
: Standby Current ( RAS=CAS=W=V
IH
)
: RAS Only Refresh Current * ( CAS=V
IH
, RAS cycling @
t
RC
=min)
: Fast Page Mode Current * ( RAS=V
IL
, CAS Address cycling :
t
PC
=min)
: Standby Current ( RAS=CAS=W=Vcc-0.2V)
: CAS-Before-RAS Refresh Current * ( RAS and CAS cycling @
t
RC
=min)
: Input Leakage Current (Any input 0
≤V
IN
≤Vcc+0.5V,
all other pins not under test=0 V)
: Output Leakage Current(Data Out is disabled, 0V
≤V
OUT
≤Vcc)
: Output High Voltage Level (I
OH
= -5mA)
: Output Low Voltage Level (I
OL
= 4.2mA)
* NOTE
: I
CC1
, I
CC3
, I
CC4
and I
CC6
are dependent on output loading and cycle rates. Specified values are obtained with the output open.
I
CC
is specified as an average current. In I
CC1
and I
CC3
, address can be changed maximum once while RAS=V
IL
. In I
CC4
,
address can be changed maximum once within one page mode cycle,
t
PC
.