INDEX
MX26C512A
512K-BIT [64K x 8] CMOS
MULTIPLE-TIME-PROGRAMMABLE EPROM
FEATURES
•
•
•
•
•
•
•
64K x 8 organization
+5V operating power supply
+12.75V program/erase voltage
Electric erase instead of UV light erase
Fast access time: 70/90/100/120/150 ns
Totally static operation
Completely TTL compatible
•
•
•
•
Operating current: 30mA
Standby current: 100uA
100 minimum erase/program cycles
Package type:
- 28 pin plastic DIP
Y
- 28 pin SOP
OG
L
- 32 pin PLCC
HNO
- 28 pin TSOP(I)
TEC
GENERAL DESCRIPTION
The MX26C512A is a 12.75V/5V, 512K-bit, MTP
EPROM
TM
(Multiple Time Programmable Read Only
Memory). It is organized as 64K words by 8 bits per word,
operates from a + 5 volt supply, has a static standby
mode, and features fast single address location program-
ming. It is designed to be reprogrammed and erased by
an EPROM programmer or on-board. All programming/
erasing signals are TTL levels, requiring a single pulse.
D
NTE
E
PAT
The MX26C512A supports an intelligent quick pulse
programming algorithm which can result in a program-
ming time of less than 30 seconds.
This MTP EPROM
TM
is packaged in industry standard 28
pin dual-in-line packages, 32 pin PLCC packages or 28
pin TSOP packages and 28 pin SOP packages.
PIN CONFIGURATIONS
PDIP/SOP
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
A14
A13
A8
A9
A11
OE/VPP
A10
CE
Q7
Q6
Q5
Q4
Q3
BLOCK DIAGRAM
PLCC
VCC
A12
A15
A14
A13
NC
A7
4
1
32
30
29
CE
OE
CONTROL
LOGIC
OUTPUT
BUFFERS
Q0~Q7
A6
A5
A4
A3
A2
A1
A0
NC
Q0
5
A8
A9
A11
NC
MX26C512A
.
.
.
A0~A15
ADDRESS
INPUTS
.
.
.
.
.
Y-DECODER
9
MX26C512A
25
OE/VPP
A10
CE
Q7
X-DECODER
.
.
.
.
.
.
.
.
Y-SELECT
512K BIT
CELL
MAXTRIX
13
14
Q1
Q2
GND
17
NC
Q3
Q4
21
20
Q5
Q6
VCC
GND
VPP
TSOP
OE/VPP
A11
A9
A8
A13
A14
VCC
A15
A12
A7
A6
A5
A4
A3
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
A10
CE
Q7
Q6
Q5
Q4
Q3
GND
Q2
Q1
Q0
A0
A1
A2
PIN DESCRIPTION
SYMBOL
A0~A15
Q0~Q7
CE
OE
VPP
NC
VCC
GND
PIN NAME
Address Input
Data Input/Output
Chip Enable Input
Output Enable Input
Program Supply Voltage
No Internal Connection
Power Supply Pin (+5V)
Ground Pin
REV.1.8, JUL. 13 , 1998
MX26C512A
P/N: PM0455
Patent#: US#5,523,307
1
INDEX
MX26C512A
FUNCTIONAL DESCRIPTION
When the MX26C512A is delivered, or it is erased, the
chip has all 512K bits in the "ONE", or HIGH state.
"ZEROs" are loaded into the MX26C512 through the
procedure of programming.
ERASE MODE
The MX26C512A is erased by EPROM programmer or
in-system. The device is set up in erase mode when
A9 =OE/VPP = 12.75V are applied, with VCC = 5V.
(Algorithm is shown in Figure 3). The erase time is around
1sec. If the erase is not verified, an additional erase
processes will be repeated for a maximum of 200 times.
PROGRAMMING MODE
PROGRAMMMING ALGORITHM
PROGRAM INHIBIT MODE
The MX26C512A is programmed by an EPROM
programmer or on-board. The device is set up in the
programming mode when the programming voltage OE/
VPP = 12.75V is applied, with VCC = 5 V (Algorithm
shown in Figure 1). Programming is achieved by applying
a single TTL low level 25us pulse to the CE input after
addresses and data lines are stable. If the data is not
verified, additional pulses are applied for a maximum of
20 pulses. After the data is verified, one 25us pulse is
applied to overprogram the byte so that program margin
is assured. This process is repeated while sequencing
through each address of the device. When programming
is completed, the data at all the addresses are verified
at VCC = 5V
±
10%.
The VCC supply of the MXIC On-Board Programming
Algorithm is designed to be 5V
±
10% particularly to
facilitate the programming operation under the on-board
application environment. But it can also be implemented
in an industrial-standard EPROM programmer.
Programming of multiple MX26C512A in parallel with
different data is also easily accomplished by using the
Program Inhibit Mode. Except for CE and OE, all like
inputs of the parallel MX26C512 may be common. A
TTL low-level program pulse applied to an MX26C512A
CE input with OE/VPP = 12.75
±
0.25 V will program
that MX26C512A. A high-level CE input inhibits the other
MX26C512A from being programmed.
PROGRAM VERIFY MODE
Verification should be performed on the programmed bits
to determine that they were correctly programmed. The
verification should be performed with OE/VPP and CE,
at VIL. Data should be verified tDV after the falling edge
of CE.
ERASE VERIFY MODE
COMPATIBILITY WITH MX27C512 FAST PROGRAMMING
ALGORITHM
Besides the On-Board Programming Algorithm, the Fast
Programming Algorithm of MX27C512 also applies to
MX26C512A. MXIC Fast Algorithm is the conventional
EPROM programing algorithm and is available in
industrial-standard EPROM programmers. A user of
industrial-standard EPROM programmer can choose
either of the algorithms base on his preference.
The device is set up in the fast programming mode when
the programming voltage OE/VPP = 12.75V isapplied,
with VCC = 6.25V, (Algorithm is shown in Figure 2). The
programming is achieved by appling a single TTL low
level 25~100us pulse to the CE input after addresses and
data line are stable. If the data is not verified, an additional
pulse is applied for a maximum of 25 pulses. This process
is repeated while sequencing through each address of
the device. When the programming mode is completed,
the data in all address is verified at VCC = 5V
±
10%.
P/N: PM0455
Patent#: US#5,523,307
Verification should be performed on the erased chip to
determine that whole chip(all bits) was correctly erased.
Verification should be performed with OE/VPP and CE
at VIL and VCC = 5V.
AUTO IDENTIFY MODE
The auto identify mode allows the reading out of a binary
code from a MTP that will identify its manufacturer and
device type. This mode is intended for use by
programming equipment for the purpose of automatically
matching the device to be programmed with its
corresponding programming algorithm. This mode is
functional in the 25°
±
5°C ambient temperature range
C
that is required when programming the MX26C512A.
To activate this mode, the programming equipment must
force 12.75V on address line A9 of the device. Two
identifier bytes may then be sequenced from the device
outputs by toggling address line A0 from VIL to VIH. All
REV.1.8, JUL. 13 , 1998
2
INDEX
MX26C512A
other address lines must be held at VIL during auto identify
mode.
Byte 0 ( A0 = VIL) represents the manufacturer code,
and byte 1 (A0 = VIH), the device identifier code. For
the MX26C512A, these two identifier bytes are given in
the Mode Select Table. All identifiers for the manufacturer
and device codes will possess odd parity, with the MSB
(DQ7) defined as the parity bit.
memory device.
SYSTEM CONSIDERATIONS
During the switch between active and standby conditions,
transient current peaks are produced on the rising and
falling edges of Chip Enable. The magnitude of these
transient current peaks is dependent on the output
capacitance loading of the device. At a minimum, a 0.1
uF ceramic capacitor (high frequency, low inherent
inductance) should be used on each device between
VCC and GND to minimize transient effects. In addition,
to overcome the voltage drop caused by the inductive
effects of the printed circuit board traces on EPROM
arrays, a 4.7 uF bulk electrolytic capacitor should be used
between VCC and GND for each of the eight devices.
The location of the capacitor should be close to where
the power supply is connected to the array.
READ MODE
The MX26C512A has two control functions, both of
which must be logically satisfied in order to obtain data
at the outputs. Chip Enable (CE) is the power control
and should be used for device selection. Output Enable
(OE) is the output control and should be used to gate
data to the output pins, independent of device selection.
Assuming that addresses are stable, address access
time (tACC) is equal to the delay from CE to output (tCE).
Data is available at the outputs tOE after the falling edge
of OE, assuming that CE has been LOW and addresses
have been stable for at least tACC - tOE.
STANDBY MODE
The MX26C512A has a CMOS standby mode which
reduces the maximum VCC current to 100 uA. It is placed
in CMOS standby when CE is at VCC
±
0.3 V. The
MX26C512A also has a TTL-standby mode which
reduces the maximum VCC current to 1.5 mA. It is placed
in TTL-standby when CE is at VIH. When in standby
mode, the outputs are in a high-impedance state,
independent of the OE input.
TWO-LINE OUTPUT CONTROL FUNCTION
To accommodate multiple memory connections, a two-
line control function is provided to allow for:
1. Low memory power dissipation,
2. Assurance that output bus contention will not occur.
It is recommended that CE be decoded and used as the
primary device-selecting function, while OE be made a
common connection to all devices in the array and
connected to the READ line from the system control bus.
This assures that all deselected memory devices are in
their low-power standby mode and that the output pins
are only active when data is desired from a particular
P/N: PM0455
Patent#: US#5,523,307
REV.1.8, JUL. 13 , 1998
3
INDEX
MX26C512A
MODE SELECT TABLE
PINS
MODE
Read
Output Disable
Standby (TTL)
Standby (CMOS)
Program
Program Verify
Erase
Erase Verify
Program Inhibit
Manufacturer Code
Device Code(26C512)
CE
VIL
VIL
VIH
VCC
VIL
VIL
VIL
VIL
VIH
VIL
VIL
OE/VPP
VIL
VIH
X
X
VPP
VIL
VPP
VIL
X
VIL
VIL
A0
X
X
X
X
X
X
X
X
X
VIL
VIH
A9
X
X
X
X
X
X
VPP
X
X
VH
VH
OUTPUTS
DOUT
High Z
High Z
High Z
DIN
DOUT
HIGH Z
DOUT
High Z
C2H
D1H
NOTES:
1. VH = 12.0V
±
0.5V
2. X = Either VIH or VIL(For auto select)
3. A1 - A8 = A10 - A15 = VIL(For auto select)
4. See DC Programming Characteristics for VPP voltage during
programming.
FIGURE 1. PROGRAMMING FLOW CHART
START
ADDRESS = FIRST LOCATION
VCC = 5V
VPP = 12.75V
X=0
PROGRAM ONE 25us PULSE
INTERACTIVE
SECTION
INCREMENT X
YES
X = 20 ?
NO
FAIL
VERIFY BYTE
?
PROGRAM ONE 25us PULSE
PASS
NO
INCREMENT ADDRESS
LAST ADDRESS
FAIL
YES
PROGRAM ONE 25us PULSE
VCC = 5V
VERIFY SECTION
VPP = VIL
VERIFY ALL BYTES
?
PASS
DEVICE PASSED
FAIL
DEVICE FAILED
P/N: PM0455
Patent#: US#5,523,307
REV.1.8, JUL. 13 , 1998
4
INDEX
MX26C512A
FIGURE 2. COMPATIBILITY WITH MX27C512 FAST PROGRAMMING FLOW CHART
START
ADDRESS = FIRST LOCATION
VCC = 6.25V
OE/VPP = 12.75V
PROGRAM ONE 25~100us PULSE
NO
INCREMENT ADDRESS
LAST
ADDRESS ?
YES
ADDRESS = FIRST LOCATION
INCREMENT ADDRESS
NO
LAST
ADDRESS ?
X=0
PASS
VERIFY BYTE
FAIL
INCREMENT X
YES
NO
PROGRAM ONE 25~100us PULSE
X = 25 ?
VCC = 5.0V
OE/VPP = VIL
YES
COMPARE
ALL BYTES
TO ORIGINAL
DATA
FAIL
DEVICE FAILED
PASS
DEVICE PASSED
P/N: PM0455
Patent#: US#5,523,307
REV.1.8, JUL. 13 , 1998
5
聊聊、笑笑、闹闹
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
