74ABT16952 16-Bit Registered Transceiver with 3-STATE Outputs
November 1993
Revised January 1999
74ABT16952
16-Bit Registered Transceiver with 3-STATE Outputs
General Description
The ABT16952 is a 16-bit registered transceiver. Two 8-bit
back to back registers store data flowing in both directions
between two bidirectional buses. Separate clock, clock
enable and 3-STATE output enable signals are provided for
each register. The output pins are guaranteed to source 32
mA and to sink 64 mA.
Features
s
Separate clock, clock enable and 3-STATE output
enable provided for each register
s
A and B output sink capability of 64 mA source capability
of 32 mA
s
Guaranteed latchup protection
s
High impedance glitch free bus loading during entire
power up and power down cycle
s
Nondestructive hot insertion capability
Ordering Code:
Order Number
74ABT16952CSSC
74ABT16952CMTD
Package Number
MS56A
MTD56
Package Description
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the letter suffix “X” to the ordering code.
Pin Descriptions
Pin Names
A
0
–A
15
B
0
–B
15
CPAB
n
, CPBA
n
CEA
n
, CEB
n
OEAB
n
, OEBA
n
Description
Data Register A Inputs/
B-Register 3-STATE Outputs
Data Register B Inputs/
A-Register 3-STATE Outputs
Clock Pulse Inputs
Clock Enable
Output Enable Inputs
Connection Diagram
Pin Assignment for SSOP
Output Control
OE
H
L
L
Internal
Q
X
L
H
Output
Z
L
H
Function
Disable Outputs
Enable Outputs
Register Function Table
(Applies to A or B Register)
Inputs
D
X
L
H
CP
CE
H
L
L
Internal
Q
NC
L
H
Function
Hold Data
Load Data
X
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
HIGH Impedance
=
LOW-to-HIGH Transition
NC
=
No Change
© 1999 Fairchild Semiconductor Corporation
DS011647.prf
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74ABT16952
Block Diagram
n for either byte 1 or byte 2
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2
74ABT16952
Absolute Maximum Ratings
(Note 1)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to
Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Any Output
in the Disable or Power-Off State
in the HIGH State
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
−0.5V
to
+5.5V
−0.5V
to V
CC
−0.5V
to
+7.0V
−0.5V
to
+7.0V
−30
mA to
+5.0
mA
−65°C
to
+150°C
−55°C
to
+125°C
−55°C
to
+150°C
DC Latchup Source Current
Over Voltage Latchup (I/O)
−500
mA
10V
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
Minimum Input Edge Rate (∆V/∆t)
Data Input
Enable Input
Clock Input
50 mV/ns
20 mV/ns
100 mV/ns
−40°C
to
+85°C
+4.5V
to
+5.5V
Note 1:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2:
Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
V
OL
V
ID
I
IH
I
BVI
I
BVIT
I
IL
I
IH
+
I
OZH
I
IL
+
I
OZL
I
OS
I
CEX
I
ZZ
I
CCH
I
CCL
I
CCZ
I
CCT
I
CCD
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
Output LOW Voltage
Input Leakage Test
Input HIGH Current
Input HIGH Current
Breakdown Test
Input HIGH Current
Breakdown Test (I/O)
Input LOW Current
Output Leakage Current
−1
−1
10
−10
−100
−275
50
100
1.0
60
1.0
2.5
No Load
0.18
mA/MHz
Max
µA
µA
mA
µA
µA
mA
mA
mA
mA
µA
Max
V
IN
=
0.5V (Non-I/O Pins) (Note 4)
V
IN
=
0.0V (Non-I/O Pins)
0V–5.5V V
OUT
=
2.7V (A
n
, B
n
);
OEA or OEB
=
2.0V
Output Leakage Current
0V–5.5V V
OUT
=
0.5V (A
n
, B
n
);
OEA or OEB
=
2.0V
Output Short-Circuit Current
Output HIGH Leakage Current
Bus Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
Additional I
CC
/Input
Dynamic I
CC
(Note 4)
Max
Max
0.0V
Max
Max
Max
Max
V
OUT
=
0V (A
n
, B
n
)
V
OUT
=
V
CC
(A
n
, B
n
)
V
OUT
=
5.5V (A
n
, B
n
);
All Others GND
All Outputs HIGH
All Outputs LOW
Outputs 3-STATE;
All Others GND
V
I
=
V
CC
−
2.1V; All Others
at V
CC
or GND
Outputs Open
OEA or OEB
=
GND,
Non-I/O
=
GND or V
CC
One Bit toggling, 50% duty cycle
(Note 3)
Note 3:
For 8-bit toggling, I
CCD
<1.4
mA/MHz.
Note 4:
Guaranteed, but not tested.
Min
2.0
Typ
Max
0.8
−1.2
Units
V
V
V
V
CC
Conditions
Recognized HIGH Signal
Recognized LOW Signal
Min
I
IN
= −18
mA (Non I/O Pins)
I
OH
= −3
mA (A
n
, B
n
)
I
OH
= −32
mA (A
n
, B
n
)
2.5
2.0
0.55
4.75
1
1
7
100
µA
µA
Max
Max
V
µA
0.0
Max
I
OL
=
64 mA (A
n
, B
n
)
I
ID
=
1.9
µA
(Non-I/O Pins)
All Other Pins Grounded
V
IN
=
2.7V (Non-I/O Pins) (Note 4)
V
IN
=
V
CC
(Non-I/O Pins)
V
IN
=
7.0V (Non-I/O Pins)
V
IN
=
5.5V (A
n
, B
n
)
3
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74ABT16952
AC Electrical Characteristics
(SSOP Package)
T
A
= +25°C
Symbol
Parameter
Min
f
max
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Max Clock
Frequency
Propagation Delay
CPAB
n
or CPBA
n
to
A
n
or B
n
Output Enable Time
OEAB
n
or OEBA
n
to
A
n
or B
n
Output Disable Time
OEAB
n
or OEBA
n
to
A
n
or B
n
1.5
1.5
6.0
6.0
1.5
1.5
6.0
6.0
ns
1.5
1.5
5.5
5.5
1.5
1.5
5.5
5.5
ns
1.5
1.5
5.3
5.3
1.5
1.5
5.3
5.3
ns
200
V
CC
= +5.0V
C
L
=
50 pF
Max
T
A
= −40°C
to
+85°C
V
CC
=
4.5V to 5.5V
C
L
=
50 pF
Min
200
Max
MHz
Units
AC Operating Requirements
T
A
= +25°C
Symbol
Parameter
Min
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
S
(H)
t
S
(L)
Setup Time, HIGH
or LOW A
n
or B
n
to CPAB
n
or CPBA
n
Hold Time, HIGH
or LOW A
n
or B
n
to CPAB
n
or CPBA
n
Setup Time, HIGH
or LOW CEA
n
or CEB
n
to CPAB
n
or CPBA
n
t
H
(H)
t
H
(L)
Hold Time, HIGH
or LOW CEA
n
or CEB
n
to CPAB
n
or CPBA
n
t
W
(H)
t
W
(L)
Pulse Width,
HIGH or LOW
to CPAB
n
or CPBA
n
3.0
3.0
3.0
3.0
ns
1.5
1.5
1.5
1.5
ns
2.5
2.5
2.5
2.5
ns
1.5
1.5
1.5
1.5
ns
2.5
2.5
V
CC
= +5.0V
C
L
=
50 pF
Max
Min
2.5
2.5
T
A
= −40°C
to
+85°C
V
CC
=
4.5V to 5.5V
C
L
=
50 pF
Max
ns
Units
Capacitance
Symbol
C
IN
C
I/O
(Note 5)
Parameter
Input Capacitance
Output Capacitance
Typ
5
11
Units
pF
pF
Conditions
T
A
=
25°C
V
CC
=
0V (Non I/O Pins)
V
CC
=
5.0V (A
n
, B
n
)
Note 5:
C
I/O
is measured at frequency f
=
1 MHz, per MIL-STD-883, Method 3012.
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4
74ABT16952
AC Loading
*Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load
Amplitude
3.0V
Rep. Rate
1 MHz
t
W
500 ns
FIGURE 2. Test Input Signal Levels
t
r
2.5 ns
t
f
2.5 ns
FIGURE 3. Input Signal Requirements
AC Waveforms
FIGURE 4. Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
FIGURE 6. 3-STATE Output HIGH
and LOW Enable and Disable Times
FIGURE 5. Propagation Delay,
Pulse Width Waveforms
FIGURE 7. Setup Time, Hold Time
and Recovery Time Waveforms
5
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