NB3V63143G
1.8 V Programmable
OmniClock Generator
with Single Ended (LVCMOS) and Differential
(LVDS/HCSL) Outputs with Individual Output
Enable and Individual VDDO
The NB3V63143G, which is a member of the OmniClock family, is
a one−time programmable (OTP), low power PLL−based clock
generator that supports any output frequency from 8 kHz to 200 MHz.
The device accepts fundamental mode parallel resonant crystal or a
single ended (LVCMOS) reference clock as input. It generates either
three single ended (LVCMOS) outputs, or one single ended output and
one differential (LVDS/HCSL) output. The output signals can be
modulated using the spread spectrum feature of the PLL
(programmable spread spectrum type, deviation and rate) for
applications demanding low electromagnetic interference (EMI).
Individual output enable pins OE[2:0] are available to enable/disable
the outputs. Individual output voltage pins VDDO[2:0] are available
to independently set the output voltage of each output. Up to four
different configurations can be written into the device memory. Two
selection pins (SEL[1:0]) allow the user to select the configuration to
use. Using the PLL bypass mode, it is possible to get a copy of the
input clock on any or all of the outputs. The device can be powered
down using the Power Down pin (PD#). It is possible to program the
internal input crystal load capacitance and the output drive current
provided by the device. The device also has automatic gain control
(crystal power limiting) circuitry which avoids the device overdriving
the external crystal.
Features
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QFN16
CASE 485AE
MARKING DIAGRAM
3V631
43Gxx
ALYWG
G
3V63143G
xx
A
L
Y
W
G
= Specific Device Code
= Specific Program Code (Default
‘00’ for Unprogrammed Part)
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information on page 20 of
this data sheet.
•
Member of the OmniClock Family of Programmable
•
•
Clock Generators
Operating Power Supply: 1.8 V
±
0.1 V
I/O Standards
♦
Inputs: LVCMOS, Fundamental Mode Crystal
♦
Outputs: 1.8 V LVCMOS
♦
Outputs: LVDS and HCSL
3 Programmable Single Ended (LVCMOS) Outputs
from 8 kHz to 200 MHz
1 Programmable Differential Clock Output up to
200 MHz
Input Frequency Range
♦
Crystal: 3 MHz to 50 MHz
♦
Reference Clock: 3 MHz to 200 MHz
Configurable Spread Spectrum Frequency Modulation
Parameters (Type, Deviation, Rate)
Individual Output Enable Pins
Independent Output Voltage Pins
•
Programmable Internal Crystal Load Capacitors
•
Programmable Output Drive Current for Single Ended
•
•
•
•
•
•
•
Outputs
Power Saving Mode through Power Down Pin
Programmable PLL Bypass Mode
Programmable Output Inversion
Programming and Evaluation Kit Available for Field
Programming and Quick Evaluation
Temperature Range −40°C to 85°C
Packaged in 16−pin QFN
These are Pb−Free Devices
•
•
•
•
•
•
Typical Applications
•
eBooks and Media Players
•
Smart Wearables, Smart Phones, Portable Medical and
Industrial Equipment
•
Set Top Boxes, Printers, Digital Cameras and
Camcorders
©
Semiconductor Components Industries, LLC, 2016
1
January, 2016 − Rev. 2
Publication Order Number:
NB3V63143G/D
NB3V63143G
BLOCK DIAGRAM
VDD
PD#
SEL0
SEL1
Input
Decoder
Output control
Crystal/Clock Control
Configuration
Memory
Frequency
and SS
Output
Divider
CMOS/
DIFF
buffer
VDDO0
CLK0
OE0
Phase
Detector
Charge
Pump
VCO
Output
Divider
Feedback
Divider
Output
Divider
PLL Bypass Mode
CMOS
buffer
CMOS/
DIFF
buffer
VDDO1
CLK1
OE1
VDDO2
CLK2
OE2
Reference
XIN/ CLKIN
Clock
Crystal
XOUT
PLL Block
Clock Buffer/
Crystal
Oscillator And
AGC
GND
GNDO
Notes:
1. CLK0 and CLK1 can be configured to be one LVDS or HCSL output, or two single ended LVCMOS outputs.
2. Dotted lines are the programmable control signals to internal IC blocks.
3. OE[2:0], SEL[1:0] have internal pull up resistors. PD# has internal pull down resistor.
Figure 1. Simplified Block Diagram
PIN FUNCTION DESCRIPTION
VDDO2
16
XIN/CLKIN
1
15
14
13
12
VDD
NB3V63143G
XOUT
CLK2
SEL0
SEL1
2
GNDO
(EPAD)
11
VDDO1
PD#
3
10
CLK1
GND
4
5
OE0
6
OE1
7
OE2
8
VDDO0
9
CLK0
Figure 2. Pin Connections (Top View) − QFN16 (with EPAD)
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NB3V63143G
Table 1. PIN DESCRIPTION
Pin No.
1
2
3
Pin Name
XIN/CLKIN
XOUT
PD#
Pin Type
Input
Output
Input
Description
3 MHz to 50 MHz crystal input connection or an external single ended reference
input clock between 3 MHz and 200 MHz.
Crystal output. Float this pin when external reference clock is connected at XIN.
Asynchronous LVCMOS input. Active Low Master Reset to disable the device and
set outputs Low. Internal pull−down resistor. This pin needs to be pulled High for
normal operation of the chip.
Power supply ground.
2−Level LVCMOS Inputs for Enabling/Disabling output clocks CLK[2:0] respectively.
Internal pull−up resistor.
CLK0 Output power supply
≤
VDD
Supports 8 kHz to 200 MHz Single Ended (LVCMOS) signals or Differential
(LVDS/HCSL) signals. Using PLL Bypass mode, the output can also be a copy of
the input clock. The single ended output will be LOW and differential outputs will be
complementary LOW/HIGH until the PLL has locked and the frequency has
stabilized.
Supports 8 kHz to 200 MHz Single Ended (LVCMOS) signals or Differential
(LVDS/HCSL) signals. Using PLL Bypass mode, the output can also be a copy of
the input clock. The single ended output will be LOW and differential outputs will be
complementary LOW/HIGH until the PLL has locked and the frequency has
stabilized.
CLK1 Output power supply
≤
VDD
1.8 V power supply.
Supports 8 kHz to 200 MHz Single Ended (LVCMOS) signals. Using PLL Bypass
mode, the output can also be a copy of the input clock. The single ended output will
be LOW until the PLL has locked and the frequency has stabilized.
CLK2 Output power supply
≤
VDD
2−Level LVCMOS Inputs for Configuration Selection. Configuration parameters
include individual output frequencies, spread spectrum configuration, enable/disable
status of each output, output type, internal crystal load capacitance configuration,
etc. Configuration can be switched dynamically, but may require the PLL to re−lock.
Internal pull−up resistor.
Power supply ground for Outputs.
4
5, 6, 7
8
9
GND
OE[2:0]
VDDO0
CLK0
Ground
Input
Power
SE/DIFF Output
10
CLK1
SE/DIFF Output
11
12
13
VDDO1
VDD
CLK2
Power
Power
SE Output
14
15, 16
VDDO2
SEL[1:0]
Power
Input
EPAD
GNDO
Ground
Table 2. OUTPUT CONFIGURATION SELECT
FUNCTION TABLE
SEL1
L
L
H
H
SEL0
L
H
L
H
Output Configuration
I
II
III
IV
Table 4. OUTPUT ENABLE FUNCTION TABLE
OE[2:0]
0
1
Function
CLK Disabled
CLK Enabled
TYPICAL CRYSTAL PARAMETERS
Crystal: Fundamental Mode Parallel Resonant
Frequency: 3 MHz to 50 MHz
Table 5. MAX CRYSTAL LOAD CAPACITORS
RECOMMENDATION
Crystal Frequency Range
3 MHz − 30 MHz
30 MHz − 50 MHz
Max Cap Value
20 pF
10 pF
Table 3. POWER DOWN FUNCTION TABLE
PD#
0
1
Function
Device Powered Down
Device Powered Up
Shunt Capacitance (C0): 7 pF (Max)
Equivalent Series Resistance 150
W
(Max)
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NB3V63143G
FUNCTIONAL DESCRIPTION
The NB3V63143G is a 1.8 V programmable, single
ended/differential clock generator, designed to meet the
timing requirements for consumer and portable markets. It
has a small package size and it requires low power during
operation and while in standby. This device provides the
1.8 V
R (Optional)
ability to configure a number of parameters as detailed in the
following section. The One−Time Programmable memory
allows programming and storing of up to four configurations
in the memory space.
VDDO0
R (Optional)
VDDO1
R (Optional)
0.1
mF
0.01
mF
0.1
mF
0.01
mF
0.1
mF
0.01
mF
Crystal or
Reference
Clock Input
VDD
XIN/CLKIN
VDDO0
VDDO1
VDDO2
R (Optional)
XOUT
NB3V63143G
SEL0
SEL1
GND
VDDO2
0.1
mF
0.01
mF
CLK2
GNDO
CLK1
CLK0
Single Ended Clock
Single Ended Clocks
or
Differential Clock
LVDS/HCSL
PD# OE0 OE1 OE2
Figure 3. Power Supply and Output Supply Noise Suppression
Power Supply
Device Supply
The NB3V63143G is designed to work with a 1.8 V VDD
power supply. For VDD operation of 3.3 V/2.5 V, refer to
the NB3H63143G datasheet. In order to suppress power
supply noise it is recommended to connect decoupling
capacitors of 0.1
mF
and 0.01
mF
close to the VDD pin as
shown in Figure 3.
Output Power Supply
power supply can be as high as VDD. This feature removes
the need for external voltage converters for each of the
outputs thus reducing component count, saving board space
and facilitating board design. In order to suppress power
supply noise it is recommended to connect decoupling
capacitors of 0.1
mF
and 0.01
mF
close to each VDDO pin as
shown in Figure 3.
Each output CLK[2:0] has a separate output power supply
VDDO[2:0] pin to control its output voltage. The output
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NB3V63143G
Clock Input
Input Frequency
The clock input block can be programmed to use
a fundamental mode crystal from 3 MHz to 50 MHz or
a single ended reference clock source from 3 MHz to
200 MHz. When using output frequency modulation for
EMI reduction, for optimal performance, it is recommended
to use crystals with a frequency greater than 6.75 MHz as
input. Crystals with ESR values of up to 150
W
are
supported. While using a crystal as input, it is important to
set crystal load capacitor values correctly to achieve good
performance.
Programmable Crystal Load Capacitors
maintain a good quality input clock signal level. This feature
takes care of low clock swings fed from external reference
clocks and ensures proper device operation. It also enables
maximum compatibility with crystals from different
manufacturers, processes, quality and performance. AGC
also takes care of power dissipation in the crystal; avoids
overdriving the crystal and thus extending the crystal life. In
order to calculate the AGC gain accurately and avoid
increasing the jitter on the output clocks, the user needs to
provide the crystal load capacitance as well as other crystal
parameters like ESR and shunt capacitance (C0).
Programmable Clock Outputs
Output Type and Frequency
The provision of internal programmable crystal load
capacitors eliminates the necessity of external load
capacitors for standard crystals. The internal load capacitors
can be programmed to any value between 4.36 pF and
20.39 pF with a step size of 0.05 pF. Refer to Table 5 for
recommended maximum load capacitor values for stable
operation. There are three modes of loading the crystal −
with internal chip capacitors only, with external capacitors
only or with the both internal and external capacitors. Check
with the crystal vendor’s load capacitance specification for
setting of the internal load capacitors. The minimum value
of 4.36 pF internal load capacitor need to be considered
while selecting external capacitor value. The internal load
capacitors will be bypassed when using an external
reference clock.
Automatic Gain Control (AGC)
The Automatic Gain Control (AGC) feature adjusts the
gain to the input clock based on its signal strength to
The NB3V63143G provides three independent single
ended LVCMOS outputs, or one single ended LVCMOS
output and one LVDS/HCSL differential output. The device
supports any single ended output or differential output
frequency from 8 kHz up to 200 MHz with or without
frequency modulation. All outputs have individual output
enable pins (refer to the Output Enable/Disable section on
page 7). It should be noted that certain combinations of
output frequencies and spread spectrum configurations may
not be recommended for optimal and stable operation.
For differential clocking, CLK0 and CLK1 can be
configured as LVDS or HCSL. While using differential
signaling format at the output, it is required to use only
VDDO1 as output supply and use only the OE1 pin for the
output enable function. (refer to the Application Schematic
in Figure 4). When all 3 outputs are single ended, VDDO0
and OE0 have normal functionality.
VDDO2
≤
VDD
Crystal or
Reference
Clock Input
VDDO2
XIN/CLKIN
CLK2
XOUT
NB3V63143G
Single Ended Clock
VDDO1
≤
VDD
VDDO1
VDDO0
CLK1
CLK0
Differential Clock
LVDS/HCSL
OE2
PD#
OE1
OE0
Figure 4. Application Setup for Differential Output Configuration
Programmable Output Drive
The drive strength or output current of each of the
LVCMOS clock outputs is programmable independently.
For each VDDO supply voltage, four distinct levels of
LVCMOS output drive strengths can be selected as
mentioned in DC Electrical Characteristics. This feature
provides further load drive and signal conditioning as per the
application requirement.
PLL BYPASS Mode
PLL Bypass mode can be used to buffer the input clock on
any of the outputs or all of the outputs. Any of the clock
outputs can be programmed to generate a copy of the input
clock.
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