FemtoClock
®
Crystal-to-LVDS
8-Output Clock Synthesizer
83908-02
Datasheet
General Description
The 83908-02 is a low skew, high performance 1-to-8 Crystal
Oscillator//Crystal-to-LVCMOS fanout buffer. The 83908-02 has
selectable single-ended clock or two crystal-oscillator inputs. There is
an output enable to disable the outputs by placing them into a
high-impedance state.
Guaranteed output and part-to-part skew characteristics make the
83908-02 ideal for those applications demanding well defined
performance and repeatability.
Features
Eight LVCMOS / LVTTL outputs, 19
typical output impedance at
V
DD
= V
DDO
= 3.3V
•
Two crystal oscillator input pairs
One LVCMOS / LVTTL clock input
•
Crystal input frequency range: 10MHz – 40MHz
•
Output frequency: 200MHz (maximum)
•
Output skew: 70ps (maximum) at V
DD
= V
DDO
= 3.3V
•
Part-to-part skew: 700ps (maximum) at V
DD
= V
DDO
= 3.3V
•
RMS phase jitter @ 25MHz output, using a 25MHz crystal,
(12kHz – 10MHz): 0.39ps (typical) at V
DD
= V
DDO
= 3.3V
•
RMS phase noise at 25MHz
Offset
Noise Power
100Hz ................. -111.4 dBc/Hz
1kHz ................. -139.9 dBc/Hz
10kHz ................. -157.3 dBc/Hz
100kHz ................. -157.5 dBc/Hz
•
Power Supply Voltage Modes:
Core / Output
3.3V / 3.3V
3.3V / 2.5V
3.3V / 1.8V
2.5V / 2.5V
2.5V / 1.8V
•
0°C to 70°C ambient operating temperature
•
Lead-free (RoHS 6) packaging
•
Block Diagram
OE
CLK_SEL0
CLK_SEL1
Pullup
Pulldown
Pulldown
Pin Assignment
VDD
XTAL_OUT0
VDDO
Q1
GND
1
3
4
5
6
7
9
10
12
24
23
22
21
20
19
18
17
16
15
14
13
GND
XTAL_IN1
XTAL_OUT1
VDDO
Q7
Q6
GND
Q5
Q4
VDDO
CLK_SEL1
OE
XTAL_IN0
OSC
0 0
Q3
VDD0
Q0
XTAL_OUT0
CLK
XTAL_IN1
83908-02
OSC
0 1
8 LVCMOS Outputs
XTAL_OUT1
Q7
CLK
Pulldown
24-Lead, 173-MIL TSSOP
4.4mm x 7.8mm x 0.925mm package body
G Package
Top View
1 0
1 1
©2016 Integrated Device Technology, Inc.
1
Revision B, April 7, 2016
83908-02 Datasheet
Pin Descriptions and Pin Characteristics
Table 1. Pin Descriptions
Number
1
2, 3
4, 10, 15, 21
5, 6, 8, 9, 16,
17, 19, 20
7, 18, 24
11,
14
12
13
22, 23
Name
V
DD
XTAL_IN0,
XTAL_OUT0
V
DDO
Q0, Q1, Q2, Q3,
Q4, Q5, Q6, Q7
GND
CLK_SEL0,
CLK_SEL1
CLK
OE
XTAL_OUT1,
XTAL_IN1
Power
Input
Power
Output
Power
Input
Input
Input
Input
Pulldown
Pulldown
Pullup
Type
Description
Power supply pin.
Crystal oscillator interface. XTAL_IN0 is the input.
XTAL_OUT0 is the output.
Output supply pins.
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Power supply ground.
Clock select inputs. See Table 3,
Input Reference Function Table.
LVCMOS/LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Output enable. When LOW, outputs are in high-impedance state.
When HIGH, outputs are active. LVCMOS/LVTTL interface levels.
Crystal oscillator interface. XTAL_IN1 is the input.
XTAL_OUT1 is the output.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation
Capacitance
(per output)
V
DDO
= 3.465V
V
DDO
= 2.625V
V
DDO
= 2.0V
V
DDO
= 3.3V ±5%
R
OUT
Output Impedance
V
DDO
= 2.5V ±5%
V
DDO
= 1.8V ±0.2V
Test Conditions
Minimum
Typical
4
51
51
7
7
6
19
21
32
Maximum
Units
pF
k
k
pF
pF
pF
C
PD
Function Table
Table 3. Input Reference Function Table
Control Inputs
CLK_SEL1
0
0
1
1
CLK_SEL0
0
1
0
1
Reference
XTAL0 enabled (default)
XTAL1 enabled
CLK enabled
CLK enabled
XTAL1 disabled
XTAL0 disabled
XTAL0 and XTAL1 disabled
XTAL0 and XTAL1 disabled
©2016 Integrated Device Technology, Inc.
2
Revision B, April 7, 2016
83908-02 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the
DC Characteristics or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DDO
+ 0.5V
87.8C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= V
DDO
= 3.3V ±5%, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Core Supply Voltage
Output Supply Voltage
No Load & XTALx selected
Power Supply Current
No Load & CLK selected
Output Supply Current
No Load & CLK selected
1
1
mA
mA
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
30
Units
V
V
mA
Table 4B. Power Supply DC Characteristics,
V
DD
= 3.3V ±5%, V
DDO
= 2.5V ±5%, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Core Supply Voltage
Output Supply Voltage
No Load & XTALx selected
Power Supply Current
No Load & CLK selected
Output Supply Current
No Load & CLK selected
1
1
mA
mA
Test Conditions
Minimum
3.135
2.375
Typical
3.3
2.5
Maximum
3.465
2.625
30
Units
V
V
mA
Table 4C. Power Supply DC Characteristics,
V
DD
= 3.3V ±5%, V
DDO
= 1.8V ±0.2V, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Core Supply Voltage
Output Supply Voltage
No Load & XTALx selected
Power Supply Current
No Load & CLK selected
Output Supply Current
No Load & CLK selected
1
1
mA
mA
Test Conditions
Minimum
3.135
1.6
Typical
3.3
1.8
Maximum
3.465
2.0
30
Units
V
V
mA
©2016 Integrated Device Technology, Inc.
3
Revision B, April 7, 2016
83908-02 Datasheet
Table 4D. Power Supply DC Characteristics,
V
DD
= V
DDO
= 2.5V ±5%, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Core Supply Voltage
Output Supply Voltage
No Load & XTALx selected
Power Supply Current
No Load & CLK selected
Output Supply Current
No Load & CLK selected
1
1
mA
mA
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
Maximum
2.625
2.625
20
Units
V
V
mA
Table 4E. Power Supply DC Characteristics,
V
DD
= 2.5V ±5%, V
DDO
= 1.8V ±0.2V, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Core Supply Voltage
Output Supply Voltage
No Load & XTALx selected
Power Supply Current
No Load & CLK selected
Output Supply Current
No Load & CLK selected
1
1
mA
mA
Test Conditions
Minimum
2.375
1.6
Typical
2.5
1.8
Maximum
2.625
2.0
20
Units
V
V
mA
Table 4F. LVCMOS/LVTTL DC Characteristics,
T
A
= 0°C to 70°C
Symbol
V
IH
Parameter
Input High Voltage
Test Conditions
V
DD
= 3.3V ±5%
V
DD
= 2.5V ±5%
Input Low Voltage
CLK,
CLK_SEL[0:1]
OE
Input
Low Current
CLK,
CLK_SEL[0:1]
OE
Output High Voltage;
NOTE 1
V
DD
= 3.3V ±5%
V
DD
= 2.5V ±5%
Input
High Current
V
DD
= 3.3V or 2.5V ±5%
V
DD
= 3.3V or 2.5V ±5%
V
DD
= 3.3V or 2.5V ±5%
V
DD
= 3.3V or 2.5V ±5%
V
DDO
= 3.3V ±5%
V
OH
V
DDO
= 2.5V ±5%
V
DDO
= 1.8V ±0.2V
V
DDO
= 3.3V ±5%
V
OL
Output Low Voltage;
NOTE 1
V
DDO
= 2.5V ±5%
V
DDO
= 1.8V ±0.2V
NOTE 1: Outputs terminated with 50 to V
DDO
/2. See Parameter Measurement section,
Load Test Circuit diagram.
-5
-150
2.6
1.8
1.2
0.6
0.5
0.4
Minimum
2.2
1.6
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
1.3
0.9
150
5
Units
V
V
V
V
µA
µA
µA
µA
V
V
V
V
V
V
V
IL
I
IH
I
IL
©2016 Integrated Device Technology, Inc.
4
Revision B, April 7, 2016
83908-02 Datasheet
Table 5. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
10
Test Conditions
Minimum
Typical
Fundamental
40
50
7
1
MHz
pF
mW
Maximum
Units
AC Electrical Characteristics
Table 6A. AC Characteristics,
V
DD
= V
DDO
= 3.3V ±5%, T
A
= 0°C to 70°C
Symbol
f
OUT
tp
LH
tsk(o)
tsk(pp)
tjit()
t
R
/ t
F
odc
t
EN
t
DIS
Parameter
Output
Frequency
w/external XTAL
w/external CLK
1.4
2.0
Test Conditions
Minimum
10
Typical
Maximum
40
200
2.6
70
700
25MHz, Integration Range:
12kHz – 10MHz
20% to 80%
38.88MHz
133MHz
200
45
47
0.39
800
55
53
10
10
Units
MHz
MHz
ns
ps
ps
ps
ps
%
%
ns
ns
Propagation Delay, Low to High;
NOTE 1
Output Skew; NOTE 2
Part-to-Part Skew; NOTE 2, 3
RMS Phase Jitter, Random;
NOTE 4
Output Rise/Fall Time
Output
Duty Cycle
w/external XTAL
w/external CLK
Output Enable Time; NOTE 5
Output Disable Time; NOTE 5
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and
with equal load conditions. Using the same type of input on each device, the output is measured at V
DDO
/2.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
©2016 Integrated Device Technology, Inc.
5
Revision B, April 7, 2016
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