Data Sheet No. PD60251
IRS2112(
-1,-2,S
)PbF
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
HIGH AND LOW SIDE DRIVER
Product Summary
V
OFFSET
I
O
+/-
V
OUT
t
on/off
(typ.)
Delay Matching
600 V max.
200 mA / 440 mA
10 V - 20 V
135 ns & 105 ns
30 ns
Floating channel designed for bootstrap operation
Fully operational to +600 V
Tolerant to negative transient voltage, dV/dt
immune
Gate drive supply range from 10 V to 20 V
Undervoltage lockout for both channels
3.3 V logic compatible
Separate logic supply range from 3.3 V to 20 V
Logic and power ground +/- 5 V offset
CMOS Schmitt-triggered inputs with pull-down
Cycle by cycle edge-triggered shutdown logic
Matched propagation delay for both channels
Outputs in phase with inputs
RoHS compliant
Packages
14-Lead PDIP
IRS2112
16-Lead PDIP
(w/o leads 4 & 5)
IRS2112-2
Description
The IRS2112 is a high voltage, high speed power
MOSFET and IGBT driver with independent high- and
low-side referenced output channels. Proprietary HVIC
and latch immune CMOS technologies enable rug-
14-Lead PDIP
gedized monolithic construction. Logic inputs are com-
(w/o lead 4)
patible with standard CMOS or LSTTL outputs, down
IRS2112-1
to 3.3 V logic. The output drivers feature a high pulse
16-Lead SOIC
current buffer stage designed for minimum driver
IRS2112S
cross-conduction. Propagation delays are matched
to simplify use in high frequency applications. The
floating channel can be used to drive an N-channel power MOSFET or IGBT in the high-side configuration
which operates up to 600 V.
Typical Connection
HO
V
DD
HIN
SD
LIN
V
SS
V
CC
V
DD
HIN
SD
LIN
V
SS
V
CC
COM
LO
V
B
V
S
up to 600 V
TO
LOAD
(Refer to Lead Assignments for correct pin configuration). This diagram shows electrical connections only. Please
refer to our Application Notes and DesignTips for proper circuit board layout.
www.irf.com
1
IRS2112(-1,-2,S)PbF
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions. Additional information is shown in Figs. 28 through 35.
Symbol
V
B
V
S
V
HO
V
CC
V
LO
V
DD
V
SS
V
IN
dV
s
/dt
P
D
R
THJA
T
J
T
S
T
L
Definition
High-side floating supply voltage
High-side floating supply offset voltage
High-side floating output voltage
Low-side fixed supply voltage
Low- side output voltage
Logic supply voltage
Logic supply offset voltage
Logic input voltage (HIN, LIN & SD)
Allowable offset supply voltage transient (Fig. 2)
Package power dissipation @ T
A
≤
+25 °C
Thermal resistance, junction to ambient
Junction temperature
Storage temperature
Lead temperature (soldering, 10 seconds)
(14 Lead DIP)
(16 Lead SOIC)
(14 Lead DIP)
(16 Lead SOIC)
Min.
-0.3
V
B
- 25
V
S
- 0.3
-0.3
-0.3
-0.3
V
CC
- 25
V
SS
- 0.3
—
—
—
—
—
—
-55
—
Max.
625
V
B
+ 0.3
V
B
+ 0.3
25
V
CC
+ 0.3
V
SS
+ 25
V
CC
+ 0.3
V
DD
+ 0.3
50
1.6
1.25
75
100
150
150
300
Units
V
V/ns
W
°C/W
°C
Recommended Operating Conditions
The input/output logic timing diagram is shown in Fig. 1. For proper operation the device should be used within the
recommended conditions. The VS and VSS offset ratings are tested with all supplies biased at 15 V differential. Typical
ratings at other bias conditions are shown in Figs. 36 and 37.
Symbol
V
B
V
S
V
HO
V
CC
V
LO
V
DD
V
SS
V
IN
T
A
Definition
High-side floating supply absolute voltage
High-side floating supply offset voltage
High-side floating output voltage
Low-side fixed supply voltage
Low- side output voltage
Logic supply voltage
Logic supply offset voltage
Logic input voltage (HIN, LIN & SD)
Ambient temperature
Min.
V
S
+ 10
Note 1
V
S
10
0
V
SS
+ 3
-5 (Note 2)
V
SS
-40
Max.
V
S
+ 20
600
V
B
20
V
CC
V
SS
+ 20
5
V
DD
125
Units
V
°C
Note 1:
Logic operational for V
S
of -5 V to +600 V. Logic state held for V
S
of -5 V to -V
BS
. (Please refer to the Design
Tip DT97-3 for more details).
Note 2:
When V
DD
< 5 V, the minimum V
SS
offset is limited to -V
DD
.
www.irf.com
2
IRS2112(-1,-2,S)PbF
Dynamic Electrical Characteristics
V
BIAS
(V
CC
, V
BS
, V
DD
) = 15 V, C
L
= 1000 pF, T
A
= 25 °C and V
SS
= COM unless otherwise specified. The dynamic
electrical characteristics are measured using the test circuit shown in Fig. 3.
Symbol
t
on
t
off
t
sd
t
r
t
f
MT
Definition
Turn-on propagation delay
Turn-off propagation delay
Shutdown propagation delay
Turn-on rise time
Turn-off fall time
Delay matching, HS & LS Turn-on/off
Min. Typ. Max. Units Test Conditions
—
—
—
—
—
—
135
130
130
75
35
—
180
160
160
130
65
30
V
S
= 600 V
V
S
= 0 V
ns
Static Electrical Characteristics
V
BIAS
(V
CC
, V
BS
, V
DD
) = 15 V, T
A
= 25 °C and V
SS
= COM unless otherwise specified. The V
IN
, V
TH
, and I
IN
parameters
are referenced to V
SS
and are applicable to all three logic input leads: HIN, LIN, and SD. The V
O
and I
O
parameters are
referenced to COM and are applicable to the respective output leads: HO or LO.
Symbol
V
IH
V
IL
V
OH
V
OL
I
LK
I
QBS
I
QCC
I
QDD
I
IN+
I
IN-
V
BSUV+
V
BSUV-
V
CCUV+
V
CCUV-
I
O+
I
O-
Definition
Logic “1” input voltage
Logic “0” input voltage
High level output voltage, V
BIAS
- V
O
Low level output voltage, V
O
Offset supply leakage current
Quiescent V
BS
supply current
Quiescent V
CC
supply current
Quiescent V
DD
supply current
Logic “1” input bias current
Logic “0” input bias current
V
BS
supply undervoltage positive going
threshold
V
BS
supply undervoltage negative going
threshold
V
CC
supply undervoltage positive going
threshold
V
CC
supply undervoltage negative going
threshold
Output high short circuit pulsed current
Output low short circuit pulsed current
Min. Typ. Max. Units Test Conditions
9.5
—
—
—
—
—
—
—
—
—
7.4
7.0
7.6
7.2
200
420
—
—
0.05
0.02
—
25
80
2.0
20
—
8.5
8.1
8.6
8.2
290
600
—
6.0
0.2
0.1
50
100
180
30
40
1.0
9.6
9.2
V
9.6
9.2
—
mA
—
V
O
= 0 V, V
IN
= V
DD
PW
≤
10 µs
V
O
= 15 V, V
IN
= 0 V
PW
≤
10 µs
µA
V
IN
= V
DD
V
IN
= 0 V
V
IN
= 0 V or V
DD
V
I
O
= 2 mA
V
B
= V
S
= 600 V
www.irf.com
3
IRS2112(-1,-2,S)PbF
Functional Block Diagram
V
B
V
DD
R Q
S
HIN
HV
LEVEL
SHIFT
UV
DETECT
PULSE
FILTER
R
R
S
Q
HO
V
DD
/V
CC
LEVEL
SHIFT
PULSE
GEN
V
S
SD
UV
DETECT
V
CC
V
DD
/V
CC
LEVEL
SHIFT
LIN
R Q
V
SS
S
LO
DELAY
COM
Lead Definitions
Symbol
V
DD
HIN
SD
LIN
V
SS
V
B
HO
V
S
V
CC
LO
COM
Description
Logic supply
Logic input for high-side gate driver output (HO), in phase
Logic input for shutdown
Logic input for low-side gate driver output (LO), in phase
Logic ground
High-side floating supply
High-side gate drive output
High-side floating supply return
Low-side supply
Low-side gate drive output
Low-side return
www.irf.com
4
IRS2112(-1,-2,S)PbF
Lead Assignments
14 Lead PDIP
16 Lead SOIC (Wide Body)
IRS2112
IRS2112S
14 Lead PDIP w/o lead 4
16 Lead PDIP w/o leads 4 & 5
IRS2112-1
Part Number
IRS2112-2
www.irf.com
5
工作这点儿事
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
