SSM3J112TU
TOSHIBA Field Effect Transistor
Silicon P-Channel MOS Type
SSM3J112TU
High Speed Switching Applications
•
•
4V drive
Low on-resistance:
R
on
= 790mΩ (max) (@V
GS
=
−4
V)
R
on
= 390mΩ (max) (@V
GS
=
−10
V)
0.65±0.05
2.1±0.1
1.7±0.1
+0.1
0.3 -0.05
3
0.166±0.05
Unit: mm
Absolute Maximum Ratings
(Ta = 25°C)
Drain-Source voltage
Gate-Source voltage
Drain current
Drain power dissipation
Channel temperature
Storage temperature range
DC
Pulse
V
DS
V
GSS
I
D
I
DP
P
D (Note 1)
P
D (Note 2)
T
ch
T
stg
−30
±
20
−1.1
−2.2
800
500
150
−55
to 150
V
V
A
mW
°C
°C
2.0±0.1
Characteristic
Symbol
Rating
Unit
1
2
0.7±0.05
Using continuously under heavy loads (e.g. the application of
high temperature/current/voltage and the significant change in
temperature, etc.) may cause this product to decrease in the
reliability significantly even if the operating conditions (i.e.
operating temperature/current/voltage, etc.) are within the
absolute maximum ratings.
Please design the appropriate reliability upon reviewing the
Toshiba Semiconductor Reliability Handbook (“Handling
Precautions”/“Derating Concept and Methods”) and individual
reliability data (i.e. reliability test report and estimated failure
rate, etc).
Note 1: Mounted on ceramic board.
2
(25.4 mm
×
25.4 mm
×
0.8 mm, Cu Pad: 645 mm )
Note 2: Mounted on FR4 board.
2
(25.4 mm
×
25.4 mm
×
1.6 mm, Cu Pad: 645 mm )
Note:
1: Gate
2: Source
3: Drain
UFM
JEDEC
JEITA
TOSHIBA
―
―
2-2U1A
Weight: 6.6 mg (typ.)
Electrical Characteristics
(Ta = 25°C)
Characteristic
Drain-Source breakdown voltage
Drain cut-off current
Gate leakage current
Gate threshold voltage
Forward transfer admittance
Drain-Source on-resistance
Input capacitance
Output capacitance
Reverse transfer capacitance
Switching time
Turn-on time
Turn-off time
Symbol
V
(BR) DSS
V
(BR) DSX
I
DSS
I
GSS
V
th
⏐Y
fs
⏐
R
DS (ON)
C
iss
C
oss
C
rss
t
on
t
off
V
DSF
Test Conditions
I
D
= −1
mA, V
GS
=
0
I
D
= −1
mA, V
GS
= +20
V
V
DS
= −30
V, V
GS
=
0
V
GS
= ±16V,
V
DS
=
0
V
DS
= −5
V, I
D
= −0.1
mA
V
DS
= −5
V, I
D
=−
0.5 A
I
D
= −0.5
A, V
GS
= −10
V
I
D
= −0.5
A, V
GS
= −4
V
(Note3)
(Note3)
(Note3)
Min
−30
−15
⎯
⎯
−0.8
0.5
⎯
⎯
⎯
⎯
⎯
⎯
⎯
(Note3)
⎯
Typ.
⎯
⎯
⎯
⎯
⎯
1.0
310
610
86
25
14
14
8.5
0.85
Max
⎯
⎯
−1
±1
−1.8
⎯
390
790
⎯
⎯
⎯
⎯
⎯
1.2
Unit
V
μA
μA
V
S
mΩ
pF
pF
pF
ns
V
V
DS
= −15
V, V
GS
=
0, f
=
1 MHz
V
DS
= −15
V, V
GS
=
0, f
=
1 MHz
V
DS
= −15
V, V
GS
=
0, f
=
1 MHz
V
DD
= −15
V, I
D
= −0.5
A,
V
GS
=
0 to
−4
V, R
G
=
10
Ω
I
D
=
1.1A, V
GS
=
0 V
Drain-Source forward voltage
Note3: Pulse test
Start of commercial production
2005-02
1
2014-03-01
SSM3J112TU
Switching Time Test Circuit
(a) Test circuit
0
IN
R
G
R
L
V
DD
−4
V
90%
OUT
(b) V
IN
0V
10%
−
4V
10
μs
(c) V
OUT
V
DS (ON)
90%
10%
t
r
t
on
t
off
t
f
V
DD
=
-10 V
R
G
=
4.7
Ω
Duty
≤
1%
V
IN
: t
r
, t
f
<
5 ns
Common Source
Ta
=
25°C
V
DD
Marking
3
Equivalent Circuit
(top view)
3
JJ5
1
2
1
2
Precaution
V
th
can be expressed as the voltage between gate and source when the low operating current value is I
D
=−0.1mA for
this product. For normal switching operation, V
GS (on)
requires a higher voltage than V
th,
and V
GS (off)
requires a lower
voltage than V
th.
(The relationship can be established as follows: V
GS (off)
< V
th
< V
GS (on)
)
Take this into consideration when using the device.
Handling Precaution
When handling individual devices which are not yet mounted on a circuit board, be sure that the environment is
protected against electrostatic discharge. Operators should wear anti-static clothing, and containers and other objects
that come into direct contact with devices should be made of anti-static materials.
2
2014-03-01
SSM3J112TU
I
D
– V
DS
−2
−10
−4.5
−4.0
Common Source
Ta
=
25°C
−10000
Common Source
VDS
= −5
V
I
D
– V
GS
−1000
(mA)
(A)
−1.5
−3.5
−1
−3.0
−0.5
VGS
= −2.5
V
−100
Drain current ID
Drain current ID
Ta
=
100°C
−25°C
−10
25°C
−1
−0.1
0
0
−0.5
−1
−1.5
−2
−0.01
0
−1
−2
−3
−4
−5
Drain-Source voltage
VDS
(V)
Gate-Source voltage
VGS (V)
R
DS (ON)
– I
D
1
Common Source
Ta
=
25°C
0.8
VGS
= −4
V
1.6
2
R
DS (ON)
– V
GS
Common Source
ID
= −0.5
A
Drain-Source on resistance
RDS (ON) (Ω)
0.6
Drain-Source on resistance
RDS (ON) (Ω)
1.2
0.4
−10
V
0.8
Ta
=
100°C
0.4
−25°C
0.2
25°C
0
0
−0.5
−1.0
−1.5
−2.0
0
0
−5
−10
−15
−20
Drain current ID (A)
Gate-Source voltage
VGS (V)
R
DS (ON)
– Ta
1.2
Common Source
ID
= −0.5
A
−3
V
th
– Ta
Common Source
VDS
= −5
V
ID
= −0.1
mA
Vth (V)
Gate threshold voltage
100
125
150
1
−2.5
Drain-Source on resistance
RDS (ON) (Ω)
0.8
VGS
= −4.0
V
−2
0.6
−10
V
0.4
−1.5
−1
0.2
−0.5
0
−25
0
25
50
75
0
−25
0
25
50
75
100
125
150
Ambient temperature Ta (°C)
Ambient temperature Ta (°C)
3
2014-03-01
SSM3J112TU
|Y
fs
| – I
D
3
500
300
1
0.3
0.1
C – V
DS
Forward transfer admittance
⎪Y
fs
⎪
(S)
(pF)
100
50
30
Ciss
Capacitance C
Coss
10
5 Common Source
3 Ta
=
25°C
f
=
1 MHz
VGS
=
0 V
1
−0.1
Crss
0.01
Common Source
0.03
0.001
−1
VDS
= −5
V
Ta
=
25°C
−10
−100
−1000
−10000
−1
−10
−100
Drain current I
D
(mA)
Drain-Source voltage
VDS
(V)
Dynamic input characteristic
−10
300
Common Source
ID
= −1
A
Ta
=
25°C
t – I
D
Common Source
VDD
= −15
V
VGS
=
0∼
−4
V
Ta
=
25°C
RG
=
10
Ω
toff
30
tf
VGS (V)
−12
V
−6
VDD
= −24
V
−4
Gate-Source voltage
Switching time t (ns)
−8
100
10
ton
tr
−2
0
0
1
2
3
3
−0.01
−0.03
−0.1
−0.3
−1
−3
Total gate charge Qg (nC)
Drain current ID (A)
I
DR
– V
DS
−2
Common Source
VGS
=
0
−1.6
Ta
=
25°C
1000
Drain power dissipation PD(mW)
800
600
a
b
PD - Ta
a: mounted on FR4 board
(25.4mm×25.4mm×1.6mm)
Cu Pad :25.4mm×25.4mm
b:mounted on ceramic board
(25.4mm×25.4mm×0.8mm)
Cu Pad :25.4mm×25.4mm
Drain reverse current IDR (A)
D
I
DR
S
G
−1.2
−0.8
400
200
0
0
20
40 60 80 100 120 140 160
Ambient temperature Ta(°C)
−0.4
0
0
0.2
0.4
0.6
0.8
1
Drain-Source voltage
VDS
(V)
4
2014-03-01
SSM3J112TU
Rth - tw
1000
Transient thermal impedance
Rth(°C/W)
c
b
a
Single pulse
a:Mounted on ceramic board
(25.4mm×25.4mm×0.8mm)
Cu Pad :25.4mm×25.4mm
b:Mounted on FR4 board
(25.4mm×25.4mm×1.6mm)
Cu Pad :25.4mm×25.4mm
c:Mounted on FR4 Board
(25.4mm×25.4mm×1.6mm)
Cu Pad :0.45mm×0.8mm×3
100
10
1
0.001
0.01
0.1
1
10
Pulse w idth tw (S)
100
1000
5
2014-03-01
嵌入式系统
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