Do Not Connect when Providing an External Clock Reference
Table 4. ATTRIBUTES
Characteristic
ESD Protection
Human Body Model
Machine Model
Value
> 8 kV
> 600 V
Level 1
UL 94 V−0 @ 0.125 in
6700 Devices
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Transistor Count
Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test
Oxygen Index: 28 to 34
1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
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2
NB3N502
Table 5. MAXIMUM RATINGS
Symbol
V
DD
V
I
T
A
T
stg
q
JA
q
JC
Parameter
Positive Power Supply
Input Voltage
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
0 LFPM
500 LFPM
(Note 1)
SOIC−8
SOIC−8
SOIC−8
Condition 1
GND = 0 V
Condition 2
Rating
7
GND – 0.5 = V
I
=
V
DD
+ 0.5
−40
to +85
−65
to +150
190
130
41 to 44
Units
V
V
°C
°C
°C/W
°C/W
°C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. JEDEC standard multilayer board
−
2S2P (2 signal, 2 power).
Table 6. DC CHARACTERISTICS
(V
DD
= 3 V to 5.5 V unless otherwise noted, GND = 0 V, T
A
=
−40°C
to +85°C) (Note 2)
Symbol
I
DD
V
OH
V
OL
V
IH
V
IL
V
IH
V
IL
V
IM
C
in
I
SC
Characteristic
Power Supply Current
(unloaded CLKOUT operating at 100 MHz with 20 MHz crystal)
Output HIGH Voltage
Output LOW Voltage
I
OH
=
−25
mA TTL High
I
OL
= 25 mA
(V
DD
/ 2) + 1
V
DD
– 0.5
0.5
V
DD
÷
2
4
±
70
V
DD
/ 2
V
DD
/ 2
(V
DD
/ 2)
−1
2.4
0.4
Min
Typ
20
Max
Unit
mA
V
V
V
V
V
V
V
pF
mA
Input HIGH Voltage, CLK only (pin 1)
Input LOW Voltage, CLK only (pin 1)
Input HIGH Voltage, S0, S1
Input LOW Voltage, S0, S1
Input level of S1 when open (Input Mid Point)
Input Capacitance, S0, S1
Output Short Circuit Current
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Parameters are guaranteed by characterization and design, not tested in production.
Table 7. AC CHARACTERISTICS
(V
DD
= 3 V to 5.5 V unless otherwise noted, GND = 0 V, T
A
=
−40°C
to +85°C) (Note 3)
Symbol
f
Xtal
f
CLK
f
OUT
Crystal Input Frequency
Clock Input Frequency
Output Frequency Range
V
DD
= 4.5 to 5.5 V (5.0 V
±
10%)
V
DD
= 3.0 to 3.6 V (3.3 V
±
10%)
Clock Output Duty Cycle at 1.5 V up to 190 MHz
Period Jitter (RMS, 1
σ)
Total Period Jitter, (peak−to−peak)
Output rise/fall time (0.8 V to 2.0 V / 2.0 V to 0.8 V)
Characteristic
Min
5
2
14
14
45
50
15
±40
1
2
Typ
Max
27
50
190
120
55
Unit
MHz
MHz
MHz
MHz
%
ps
ps
ns
DC
t
jitter (rms)
t
jitter (pk−to−pk)
t
r
/t
f
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Parameters are guaranteed by characterization and design, not tested in production.
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3
NB3N502
APPLICATIONS INFORMATION
High Frequency CMOS/TTL Oscillators
Series Termination Resistor Recommendation
The NB3N502, along with a low frequency fundamental
mode crystal, can build a high frequency CMOS/TTL output
oscillator. For example, a 20 MHz crystal connected to the
NB3N502 with the 5X output selected (S1 = L, S0 = H)
produces a 100 MHz CMOS/TTL output clock.
External Components
Decoupling Instructions
A 33
W
series terminating resistor can be used on the
CLKOUT pin.
Crystal Load Capacitors Selection Guide
In order to isolate the NB3N502 from system power
supply, noise de−coupling is required. The 0.01
mF
decoupling capacitor has to be connected between V
DD
and
GND on pins 2 and 3. It is recommended to place
de−coupling capacitors as close as possible to the NB3N502
device to minimize lead inductance. Control input pins can
be connected to device pins V
DD
or GND, or to the V
DD
and
GND planes on the board.
The total on−chip capacitance is approximately 12 pF per
pin (C
IN1
and C
IN2
). A parallel resonant, fundamental mode
crystal should be used.
The device crystal connections should include pads for
small capacitors from X1/CLK to ground and from X2 to
ground. These capacitors, C
L1
and C
L2
, are used to adjust the
stray capacitance of the board to match the nominally
required crystal load capacitance (C
LOAD
(crystal)).
Because load capacitance can only be increased in this
trimming process, it is important to keep stray capacitance
to a minimum by using very short PCB traces (and no vias)
between the crystal and device. Crystal load capacitors, if
needed, must be connected from each of the pins X1 and X2
to ground. The load capacitance of the crystal (C
LOAD
(crystal)) must be matched by total load capacitance of the
oscillator circuitry network, C
INX
, C
SX
and C
LX
, as seen by
the crystal (see Figure 3 and equations below).
C
LOAD1
= C
IN1
+ C
S1
+ C
L1
[Total capacitance on X1/CLK]
C
LOAD2
= C
IN2
+ C
S2
+ C
L2
[Total capacitance on X2]
C
IN1
[
C
IN2
[
12 pF (Typ) [Internal capacitance]
C
S1
[
C
S2
[
5 pF (Typ) [External PCB stray capacitance]
C
LOAD1,2
= 2
S
C
LOAD
(Crystal)
C
L2
= C
LOAD2
−
C
IN2
−
C
S2
[External load capacitance on X2]
C
L1
= C
LOAD1
−
C
IN1
−
C
S1
[External load capacitance on X1/CLK]
Internal
to Device
R
G
C
IN1
12 pF
C
IN2
12 pF
X1/CLK
C
S1
C
S2
X2
Example 1: Equal stray capacitance on PCB
C
LOAD
(Crystal) = 18 pF (Specified by the crystal manufacturer)
C
LOAD1
= C
LOAD2
= 36 pF
C
IN1
= C
IN2
= 12 pF
C
S1
= C
S2
= 6 pF
C
L1
= 36
−
12
−
6 = 18 pF
C
L2
= 36
−
12
−
6 = 18 pF
Example 2: Different stray capacitance on PCB trace X1/CLK vs. X2
C
LOAD
(Crystal) = 18 pF
C
LOAD1
= C
LOAD2
= 36 pF
C
IN1
= C
IN2
= 12 pF
C
S1
= 4 pF & C
S2
= 8 pF
C
L1
= 36
−
12
−
4 = 20 pF
C
L2
= 36
−
12
−
8 = 16 pF
C
L1
C
L2
Crystal
Figure 3. Using a Crystal as Reference Clock
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4
NB3N502
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
−X−
A
8
5
B
1
S
4
0.25 (0.010)
M
Y
M
−Y−
G
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
DIM
A
B
C
D
G
H
J
K
M
N
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0
_
8
_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0
_
8
_
0.010
0.020
0.228
0.244
C
−Z−
H
D
0.25 (0.010)
M
SEATING
PLANE
N
X 45
_
0.10 (0.004)
M
J
Z Y
S
X
S
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm
inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor
and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone:
303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax:
303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email:
orderlit@onsemi.com
N. American Technical Support:
800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
ON Semiconductor Website: www.onsemi.com
Order Literature:
http://www.onsemi.com/orderlit
For additional information, please contact your local
我的PB用2410的BSP就可以编译通过，用2440的老是出现这样的问题，怎么回事呢？
BUILD: NMAKE : U1073: don't know how to make 'F:\WINCE500\PBWorkspaces\2440\WINCE500\smdk2440_ARMV4I\ce ......
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