notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the
latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can rea-
sonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applica-
tions unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A1
10/11/2016
1
IS42S16100H, IS45S16100H
PIN CONFIGURATIONS
50-Pin TSOP (Type II)
VDD
DQ0
DQ1
GNDQ
DQ2
DQ3
VDDQ
DQ4
DQ5
GNDQ
DQ6
DQ7
VDDQ
LDQM
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
GND
DQ15
DQ14
GNDQ
DQ13
DQ12
VDDQ
DQ11
DQ10
GNDQ
DQ9
DQ8
VDDQ
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
GND
PIN DESCRIPTIONS
A0-A10
A11
A0-A7
DQ0 to DQ15
CLK
CKE
CS
RAS
Row Address Input
Bank Select Address
Column Address Input
Data DQ
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
CAS
WE
LDQM
VDD
GND
VDDQ
NC
Column Address Strobe Command
Write Enable
Lower Bye, Input/Output Mask
Power
Ground
Power Supply for DQ Pin
No Connection
UDQM Upper Bye, Input/Output Mask
GNDQ Ground for DQ Pin
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A1
10/11/2016
IS42S16100H, IS45S16100H
PIN CONFIGURATION
package code: B 60 BaLL Tf-Bga (Top View) (10.1 mm x 6.4 mm Body, 0.65 mm Ball pitch)
1 2 3 4 5 6 7
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
PIN DESCRIPTIONS
a0-a10
a0-a7
a11
dQ0 to dQ15
cLk
cke
CS
RAS
CAS
Row address Input
column address Input
Bank Select address
data I/o
System clock Input
clock enable
chip Select
Row address Strobe command
column address Strobe command
WE
LdQM, UdQM
V
dd
gNd
V
ddq
gNd
q
Nc
Write enable
x16 Input/output Mask
power
ground
power Supply for I/o pin
ground for I/o pin
No connection
GND DQ15
DQ14 GND
DQ13 VDDQ
DQ12 DQ11
DQ10 GNDQ
DQ9 VDDQ
DQ8
NC
NC
NC
DQ0
VDD
VDDQ DQ1
GNDQ DQ2
DQ4
DQ3
VDDQ DQ5
GNDQ DQ6
NC
VDD
LDQM
RAS
NC
NC
A0
A2
A3
DQ7
NC
WE
CAS
CS
NC
A10
A1
VDD
NC UDQM
NC
CKE
A11
A8
A6
GND
CLK
NC
A9
A7
A5
A4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A1
10/11/2016
3
IS42S16100H, IS45S16100H
PIN FUNCTIONS
TSOP Pin No. Symbol
20 to 24
27 to 32
A0-A10
Type
Input Pin
Function (In Detail)
A0 to A10 are address inputs. A0-A10 are used as row address inputs during active
command input and A0-A7 as column address inputs during read or write command input.
A10 is also used to determine the precharge mode during other commands. If A10 is
LOW during precharge command, the bank selected by A11 is precharged, but if A10 is
HIGH, both banks will be precharged.
When A10 is HIGH in read or write command cycle, the precharge starts automatically
after the burst access.
These signals become part of the OP CODE during mode register set command input.
A11 is the bank selection signal. When A11 is LOW, bank 0 is selected and when high,
bank 1 is selected. This signal becomes part of the OP CODE during mode register set
command input.
CAS,
in conjunction with the
RAS
and
WE,
forms the device command. See the
“Command Truth Table” item for details on device commands.
The CKE input determines whether the CLK input is enabled within the device. When is
CKE HIGH, the next rising edge of the CLK signal will be valid, and when LOW, invalid.
When CKE is LOW, the device will be in either the power-down mode, the clock suspend
mode, or the self refresh mode. The CKE is an asynchronous input.
CLK is the master clock input for this device. Except for CKE, all inputs to this device are
acquired in synchronization with the rising edge of this pin.
The CS input determines whether command input is enabled within the device.
Command input is enabled when
CS is LOW, and disabled with CS is HIGH. The device
remains in the previous state when
CS is HIGH.
DQ0 to DQ15 are DQ pins. DQ through these pins can be controlled in byte units
using the LDQM and UDQM pins.
LDQM and UDQM control the lower and upper bytes of the DQ buffers. In read
mode, LDQM and UDQM control the output buffer. When LDQM or UDQM is LOW, the
corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go to
the HIGH impedance state when LDQM/UDQM is HIGH. This function corresponds to OE
in conventional DRAMs. In write mode, LDQM and UDQM control the input buffer. When
LDQM or UDQM is LOW, the corresponding buffer byte is enabled, and data can be
written to the device. When LDQM or UDQM is HIGH, input data is masked and cannot be
FPGA/CPLD
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