A43L2632
Preliminary
Features
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks / Pulse
RAS
MRS cycle with address key programs
- CAS Latency (2,3)
- Burst Length (1,2,4,8 & full page)
-
Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the
system clock
Deep Power Down Mode
Burst Read Single-bit Write operation
Clock Frequency (max) : 166MHz @ CL=3 (-6)
143MHz @ CL=3 (-7)
1M X 32 Bit X 4 Banks Synchronous DRAM
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle)
Self refresh with programmable refresh period through
EMRS cycle
Programmable Power Reduction Feature by partial array
activation during Self-refresh through EMRS cycle
86 Pin TSOP (II)
operating temperature range: 0ºC to + 70ºC
General Description
The A43L2632 is 67,108,864 bits Low Power synchronous
high data rate Dynamic RAM organized as 4 X 1,048,576
words by 32 bits, fabricated with AMIC’s high performance
CMOS technology. Synchronous design allows precise
cycle control with the use of system clock. I/O transactions
are possible on every clock cycle. Range of operating
frequencies, programmable latencies allows the same
device to be useful for a variety of high bandwidth, high
performance memory system applications.
PRELIMINARY
(January, 2005, Version 0.0)
1
AMIC Technology, Corp.
A43L2632
Pin Descriptions
Symbol
Name
Description
CLK
CS
System Clock
Chip Select
Active on the positive going edge to sample all inputs.
Disables or Enables device operation by masking or enabling all inputs except CLK,
CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE
Clock Enable
CKE should be enabled at least one clock + tss prior to new command.
Disable input buffers for power down in standby.
Row / Column addresses are multiplexed on the same pins.
A0~A11
Address
Row address : RA0~RA11, Column address: CA0~CA7
Selects bank to be activated during row address latch time.
BS0, BS1
Bank Select Address
Selects band for read/write during column address latch time.
Row Address Strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Column Address
Strobe
Write Enable
Data Input/Output
Mask
Data Input/Output
Power
Supply/Ground
Data Output
Power/Ground
No Connection
RAS
Latches column addresses on the positive going edge of the CLK with
CAS
low.
Enables column access.
Enables write operation and Row precharge.
Makes data output Hi-Z, t SHZ after the clock and masks the output.
Blocks data input when DQM
0-3
active.
Data inputs/outputs are multiplexed on the same pins.
Power Supply: +3.3V
±
0.125V/Ground
Provide isolated Power/Ground to DQs for improved noise immunity.
CAS
WE
DQM
0-3
DQ
0-31
VDD/VSS
VDDQ/VSSQ
NC/RFU
PRELIMINARY
(January, 2005, Version 0.0)
4
AMIC Technology, Corp.
FPGA/CPLD
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