A45L9332A Series
Preliminary
Document Title
256K X 32Bit X 2 Banks Synchronous Graphic RAM
Revision History
Rev. No.
0.0
0.1
256K X 32 Bit X 2 Banks Synchronous Graphic RAM
History
Initial issue
Update AC and DC data specification
Issue Date
August 21, 2001
October 22, 2001
Remark
Preliminary
PRELIMINARY
(October, 2001, Version 0.1)
AMIC Technology, Inc.
A45L9332A Series
Preliminary
Features
n
n
n
n
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Dual banks / Pulse RAS
MRS cycle with address key programs
- CAS Latency (2,3)
- Burst Length (1,2,4,8 & full page)
-
Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the
system clock
Burst Read Single-bit Write operation
DQM 0-3 for byte masking
Auto & self refresh
32ms refresh period (2K cycle)
n
100 Pin QFP, LQFP (14 X 20 mm)
256K X 32 Bit X 2 Banks Synchronous Graphic RAM
Graphics Features
n
SMRS cycle
- Load mask register
- Load color register
n
Write Per Bit (Old Mask)
n
Block Write (8 Columns)
n
n
n
n
n
General Description
The A45L9332A is 16,777,216 bits synchronous high data
rate Dynamic RAM organized as 2 X 262,144 words by 32
bits, fabricated with AMIC’s high performance CMOS
technology. Synchronous design allows precise cycle
control with the use of system clock. I/O transactions are
possible on every clock cycle. Range of operating
frequencies, programmable latencies allows the same
device to be useful for a variety of high bandwidth, high
performance memory system applications.
Write per bit and 8 columns block write improves
performance in graphics system.
PRELIMINARY
(October, 2001, Version 0.1)
1
AMIC Technology, Inc.
A45L9332A Series
Pin Configuration
VSSQ
DQ
31
DQ
30
VSSQ
82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
DQ
3
VDDQ
DQ
4
DQ
5
VSSQ
DQ
6
DQ
7
VDDQ
DQ
16
DQ
17
VSSQ
DQ
18
DQ
19
VDDQ
VDD
VSS
DQ
20
DQ
21
VSSQ
DQ
22
DQ
23
VDDQ
DQM
0
DQM
2
WE
CAS
RAS
CS
BA(A10)
A8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
81
80
79
78
77
76
75
74
73
72
71
70
69
DQ
29
VDD
VSS
DQ
2
DQ
1
DQ
0
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DQ
28
VDDQ
DQ
27
DQ
26
VSSQ
DQ
25
DQ
24
VDDQ
DQ
15
DQ
14
VSSQ
DQ
13
DQ
12
VDDQ
VSS
VDD
DQ
11
DQ
10
VSSQ
DQ
9
DQ
8
VDDQ
NC
DQM
3
DQM
1
CLK
CKE
DSF
NC
A9
A45L9332AE
A45L9332AF
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A0
A1
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
A2
A4
A5
A6
VDD
A3
A7
PRELIMINARY
(October, 2001, Version 0.1)
2
AMIC Technology, Inc.
A45L9332A Series
Block Diagram
DQMi
BLOCK
WRITE
CONTROL
LOGIC
CLK
MASK
REGISTER
WRITE
CONTROL
LOGIC
MASK
CLOCK
REGISTER
MUX
INPUT BUFFER
CKE
COLUMN
MASK
DQMi
TIMMING REGISTER
DQi
(i=0~31)
CS
RAS
SENSE AMPLIFIER
LATENCY &
BURST LENGTH
PROGRAMING
REGISTER
CAS
256K x 32
CELL
ARRAY
256K x 32
CELL
ARRAY
WE
DSF
ROW DECORDER
BANK SELECTION
DQMi
SERIAL
COUNTER
COLUMN ADDRESS
BUFFER
ROW
ADDRESS
BUFFER
REFRESH
COUNTER
ADDRESS REGISTER
CLOCK
ADDRESS (A0~A10)
PRELIMINARY
(October, 2001, Version 0.1)
3
AMIC Technology, Inc.
INPUT BUFFER
COLUMN
DECORDER
A45L9332A Series
Pin Descriptions
Symbol
CLK
CS
Name
System Clock
Chip Select
Description
Active on the positive going edge to sample all inputs.
Disables or Enables device operation by masking or enabling all inputs except
CLK, CKE and DQMi
Masks system clock to freeze operation from the next clock cycle.
CKE
Clock Enable
CKE should be enabled at least one clock + t ss prior to new command.
Disable input buffers for power down in standby.
Row / Column addresses are multiplexed on the same pins.
A0~A9
Address
Row address : RA0~RA9, Column address: CA0~CA7
Selects bank to be activated during row address latch time.
A10(BA)
Bank Select Address
Selects band for read/write during column address latch time.
RAS
Row Address Strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
WE
DQMi
DQi
DSF
VDD/VSS
VDDQ/VS
SQ
NC
Write Enable
Enables write operation and Row precharge.
Makes data output Hi-Z, t SHZ after the clock and masks the output.
Data Input/Output Mask
Blocks data input when DQM active. (Byte Masking)
Data Input/Output
Define Special Function
Power Supply/Ground
Data Output
Power/Ground
No Connection
Data inputs/outputs are multiplexed on the same pins.
Enables write per bit, block write and special mode register set.
Power Supply: +3.3V±0.3V/Ground
Provide isolated Power/Ground to DQs for improved noise immunity.
CAS
Column Address Strobe
PRELIMINARY
(October, 2001, Version 0.1)
4
AMIC Technology, Inc.
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