SN74SSQEC32882: 产品描述SN74SSQEC32882 JEDEC SSTE32882 Compliant Low Power 28-Bit to 56-Bit Registered Buffer with Address-Parity Test; 产品类别半导体模拟混合信号IC; 文件大小700KB，共9页; 制造商Texas Instruments(德州仪器); 官网地址http://www.ti.com.cn/; 标准

敬请期待详细参数

SN74SSQEC32882概述

SN74SSQEC32882 JEDEC SSTE32882 Compliant Low Power 28-Bit to 56-Bit Registered Buffer with Address-Parity Test

SN74SSQEC32882规格参数

参数名称	属性值
Absolute jitter (peak-to-peak cycle or period jitter)(ps)	30
Package Group	NFBGA\|176
Operating frequency range(Min)(MHz)	300
Rating	Catalog
Approx. price(US$)	3.90 \| 1ku
Operating frequency range(Max)(MHz)	945
Output drive(mA)	N/A
Function	DDR3 Register
VCC(V)	1.35
Number of outputs	60
tsk(o)(ps)	N/A
Operating temperature range(C)	0 to 85
t(phase error)(ps)	N/A

器件捷径: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

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