SN74SSQEA32882: 产品描述SN74SSQEA32882 JEDEC SSTE32882 Compliant 28-Bit to 56-Bit Registered Buffer with Address-Parity Test; 产品类别半导体模拟混合信号IC; 文件大小712KB，共13页; 制造商Texas Instruments(德州仪器); 官网地址http://www.ti.com.cn/; 标准

敬请期待详细参数

SN74SSQEA32882概述

SN74SSQEA32882 JEDEC SSTE32882 Compliant 28-Bit to 56-Bit Registered Buffer with Address-Parity Test

SN74SSQEA32882规格参数

参数名称	属性值
Package Group	NFBGA\|176
Operating frequency range(Min)(MHz)	300
Rating	Catalog
Approx. price(US$)	3.90 \| 1ku
Output drive(mA)	N/A
Function	DDR3 Register
VCC(V)	1.35
Absolute jitter (peak-to-peak cycle or period jitter)(ps)	40
Number of outputs	60
Operating frequency range(Max)(MHz)	810
tsk(o)(ps)	N/A
Operating temperature range(C)	0 to 85
t(phase error)(ps)	N/A

器件捷径: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

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