+5 V power supply. All pins must be be updated on each clock cycle. When
connected.
ENB
N
is LOW, registers D
N
and C
N
are
both strobed by the next rising edge of
Clock
CLK. When ENB
N
is HIGH and ENSEL
CLK — Master Clock
is LOW, register D
N
is strobed while
The rising edge of CLK strobes all en- register C
N
is held. If both ENB
N
and
abled registers. All timing specifica- ENSEL are HIGH, register D
N
is held,
tions are referenced to the rising edge of and register C
N
is strobed (Table 1).
CLK.
ENSEL — Enable Select
When the FSEL input is LOW, the data
input during the current clock cycle is
assumed to be in fractional two’s
complement format, and the upper 16
bits of the accumulator are presented at
the output. Rounding of the accumula-
tor result to 16 bits is performed if the
accumulator control input ACC is
LOW. When FSEL is HIGH, the data
input is assumed to be in integer two’s
complement format, and the lower 16
bits of the accumulator are presented at
the output. No rounding is performed
when FSEL is HIGH.
ACC — Accumulator Control
Inputs
D1
9–0
–D4
9–0
— Data Input
D1–D4 are 10-bit data input registers.
The LSB is D
N0
(Figure 1a).
C1
10–0
–C4
10–0
— Coefficient Input
C1–C4 are 11-bit coefficient input regis-
ters. The LSB is C
N0
(Figure 1a).
Outputs
S
15–0
— Data Output
The current 16-bit result is available on
the S
15–0
outputs (Figure 1b).
The ACC input determines whether in-
ternal accumulation is performed on
the data input during the current clock
cycle. If ACC is LOW, no accumulation
is performed, the prior accumulated
sum is cleared, and the current sum of
products is output. If FSEL is also LOW,
OEN — Output Enable
When the OEN signal is LOW, the cur- one-half LSB rounding to 16 bits is per-
rent data in the output register is avail- formed on the result. This allows sum-
able on the S
15–0
pins. When OEN is mations without propagating roundoff
HIGH, the outputs are in a high-imped- errors. When ACC is HIGH, the emerg-
ing product is added to the sum of the
ance state.
previous products, without additional
rounding.
The ENSEL input in conjunction with
the individual input enables ENB1–
ENB4 determines whether the data or
the coefficient input registers will be
held on the next rising edge of CLK
(Table 1).
Video Imaging Products
2-12
08/16/2000–LDS.2246-K
LF2246
DEVICES INCORPORATED
11 x 10-bit Image Filter
M
AXIMUM
R
ATINGS
Above which useful life may be impaired (Notes 1, 2, 3, 8)
Storage temperature ........................................................................................................... –65°C to +150°C
Operating ambient temperature ........................................................................................... –55°C to +125°C
V
CC
supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V
Input signal with respect to ground ............................................................................... –0.5 V to V
CC
+ 0.5 V
Signal applied to high impedance output ...................................................................... –0.5 V to V
CC
+ 0.5 V
Output current into low outputs ............................................................................................................. 25 mA
Latchup current ............................................................................................................................... > 400 mA
O
PERATING
C
ONDITIONS
To meet specified electrical and switching characteristics
Mode
Active Operation, Commercial
Active Operation, Military
Temperature Range
(Ambient)
0°C to +70°C
–55°C to +125°C
Supply
Voltage
4.75 V
≤
V
CC
≤
5.25 V
4.50 V
≤
V
CC
≤
5.50 V
E
LECTRICAL
C
HARACTERISTICS
Over Operating Conditions (Note 4)
Symbol
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC1
I
CC2
C
IN
C
OUT
Parameter
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Input Current
Output Leakage Current
V
CC
Current, Dynamic
V
CC
Current, Quiescent
Input Capacitance
Output Capacitance
(Note 3)
Test Condition
V
CC
= Min.,
I
OH
= –2.0 mA
V
CC
= Min.,
I
OL
= 4.0 mA
Min
2.4
Typ
Max
Unit
V
0.4
2.0
0.0
V
CC
0.8
±10
±40
100
6
10
10
V
V
V
µA
µA
mA
mA
pF
pF
Ground
≤
V
IN
≤
V
CC
(Note 12)
(Note 12)
(Notes 5, 6)
(Note 7)
T
A
= 25°C, f = 1 MHz
T
A
= 25°C, f = 1 MHz
Video Imaging Products
2-13
08/16/2000–LDS.2246-K
432109876543210987654321
432109876543210987654321
432109876543210987654321
*D
ISCONTINUED
S
PEED
G
RADE
Symbol
Symbol
S
15-0
HIGH IMPEDANCE
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7654321098765432121098765432109876543210987654321
7654321098765432121098765432109876543210987654321
432109876543210987654321
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432109876543210987654321
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432109876543210987654321
DEVICES INCORPORATED
S
WITCHING
W
AVEFORMS
M
ILITARY
O
PERATING
R
ANGE
(–55°C to +125°C)
Notes 9, 10 (ns)
C
OMMERCIAL
O
PERATING
R
ANGE
(0°C to +70°C)
Notes 9, 10 (ns)
SWITCHING CHARACTERISTICS
t
ENA
t
DIS
t
D
t
H
t
S
t
PWH
t
PWL
t
CYC
t
ENA
t
DIS
t
D
t
H
t
S
t
PWH
t
PWL
t
CYC
C1
10-0
– C4
10-0
CONTROLS
(Except OEN)
D1
9-0
– D4
9-0
OEN
CLK
Three-State Output Enable Delay
(Note 11)
Three-State Output Disable Delay
(Note 11)
Output Delay
Input Hold Time
Input Setup Time
Clock Pulse Width High
Clock Pulse Width Low
Cycle Time
Parameter
Parameter
Three-State Output Enable Delay
(Note 11)
Three-State Output Disable Delay
(Note 11)
Output Delay
Input Hold Time
Input Setup Time
Clock Pulse Width High
Clock Pulse Width Low
Cycle Time
t
S
C
N
D
N
1
t
H
D
N+1
C
N+1
2
t
DIS
t
PWH
2-14
3
t
ENA
t
PWL
Min
10
15
33
10
0
33*
4
Max
15
15
15
S
N–1
Video Imaging Products
11 x 10-bit Image Filter
Min
Min
10
15
33
10
10
10
25
0
0
8
LF2246–
25
t
D
33*
5
Max
Max
15
15
15
15
15
13
LF2246–
S
N
Min
Min
10
10
25
15
08/16/2000–LDS.2246-K
0
8
7
0
7
5
6
25*
LF2246
15
S
N+1
Max
Max
15
15
13
15
15
11
LF2246
DEVICES INCORPORATED
11 x 10-bit Image Filter
NOTES
9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
t
DIS
test), and input levels of nominally
0 to 3.0 V. Output loading may be a
resistive divider which provides for
specified
I
OH
and
I
OL
at an output
voltage of
V
OH
min and
V
OL
max
2. The products described by this spec- respectively. Alternatively, a diode
ification include internal circuitry de- bridge with upper and lower current
signed to protect the chip from damag-
sources of
I
OH
and
I
OL
respectively,
ing substrate injection currents and ac- and a balancing voltage of 1.5 V may be
cumulations of static charge. Neverthe- used. Parasitic capacitance is 30 pF
less, conventional precautions should minimum, and may be distributed.
be observed during storage, handling,
and use of these circuits in order to This device has high-speed outputs ca-
avoid exposure to excessive electrical pable of large instantaneous current
stress values.
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in the
3. This device provides hard clamping of testing of this device. The following
transient undershoot and overshoot. In- measures are recommended:
put levels below ground or above
V
CC
will be clamped beginning at –0.6 V and a. A 0.1 µF ceramic capacitor should be
V
CC
+ 0.6 V. The device can withstand installed between
V
CC
and Ground
indefinite operation with inputs in the leads as close to the Device Under Test
range of –0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors
tion will not be adversely affected, how- should be installed between device
V
CC
ever, input current levels will be well in and the tester common, and device
ground and tester common.
excess of 100 mA.
4. Actual test conditions may vary from b. Ground and
V
CC
supply planes
those designated but operation is guar- must be brought directly to the DUT
anteed as specified.
socket or contactor fingers.
5. Supply current for a given applica- c. Input voltages should be adjusted to
tion can be accurately approximated by: compensate for inductive ground and
V
CC
noise to maintain required DUT input
2
F
NCV
levels relative to the DUT ground pin.
where
4
10. Each parameter is shown as a min-
imum or maximum value. Input re-
quirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the exter-
6. Tested with all outputs changing ev- nal system must supply at least that
ery cycle and no load, at a 30 MHz clock much time to meet the worst-case re-
quirements of all parts. Responses from
rate.
the internal circuitry are specified from
7. Tested with all inputs within 0.1 V of the point of view of the device. Output
V
CC
or Ground, no load.
delay, for example, is specified as a
8. These parameters are guaranteed maximum since worst-case operation of
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