LF3347
DEVICES INCORPORATED
High-Speed Image Filter with Coefficient RAM
LF3347
DEVICES INCORPORATED
High-Speed Image Filter with Coefficient RAM
DESCRIPTION
The
LF3347
consists of an array of
four 12 x 12-bit registered multipliers
followed by two summers and a
32-bit accumulator. The LF3347
provides four 256 x 12-bit coefficient
banks which are capable of storing
256 different sets of filter coefficients
for the multiplier array. All multi-
plier data inputs are user accessible
and can be updated every clock cycle
with two’s complement data. The
pipelined architecture has fully
registered input and output ports and
an asynchronous three-state output
enable control to simplify the design
of complex systems.
A 32-bit accumulator allows cumula-
tive word growth which may be
internally rounded to 16-bits. Output
data is updated every clock cycle and
may be held under user control. The
data inputs/outputs and control
inputs are registered on the rising
edge of CLK. The Control/Coeffi-
cient Data Input,
CC
11-0
, is registered
on the rising edge of CCCLK.
The LF3347 is ideal for performing
pixel interpolation in image manipu-
lation and filtering applications. The
LF3347 can perform a bilinear inter-
polation of an image (4-pixel kernels)
at real-time video rates when used
FEATURES
u
83 MHz Data Input and Compu-
tation Rate
u
Four 12 x 12-bit Multipliers with
Individual Data and Coefficient
Inputs
u
Four 256 x 12-bit Coefficient Banks
u
32-bit Accumulator
u
Selectable 16-bit Data Output with
User-Defined Rounding and Limiting
u
u
u
u
Two’s Complement Operands
3.3 Volt Power Supply
5 Volt Tolerant I/O
120-pin PQFP
LF3347 B
LOCK
D
IAGRAM
12
CC
11-0
LD
CCCLK
ENBA
8
A
7-0
Coefficient
Bank 1
(256 x 12-bit)
ENB
1
12
2
D2
11-0
12
2
ENB
2
12
Coefficient
Bank 2
(256 x 12-bit)
D3
11-0
12
2
ENB
3
12
Coefficient
Bank 3
(256 x 12-bit)
D4
11-0
12
2
ENB
4
12
Coefficient
Bank 4
(256 x 12-bit)
LF
INTERFACE
D1
11-0
12
25
25
ACC
3
32
SELRND
3-0
4
4
4
Rounding
Selecting
Limiting
Circuit
Rounding/
Limiting
Registers
SELLMT
3-0
4
6
4
LMTEN
6
SHIFT
4-0
5
5
5
16
OCEN
OE
16
CLK
TO ALL REGISTERS
S
15-0
NOTE: NUMBERS IN REGISTERS INDICATE
NUMBER OF PIPELINE DELAYS
Video Imaging Products
1
08/16/2000–LDS.3347-G
LF3347
DEVICES INCORPORATED
High-Speed Image Filter with Coefficient RAM
F
IGURE
1.
I
NPUT
F
ORMATS
Data
Coefficient
Fractional Two's Complement
11 10 9
–2
0
2
–1
2
–2
(Sign)
with an image resampling se-
quencer. Larger kernels or more
complex functions can be realized
by utilizing multiple devices.
Unrestricted access to all data
ports and addressable coefficient
banks provides the LF3347 with
considerable flexibility in applica-
tions such as digital filters, adap-
tive FIR filters, mixers, and other
similar systems requiring high-
speed processing.
SIGNAL DEFINITIONS
Power
V
CC
and GND
+3.3 V power supply. All pins must
be connected.
Clocks
CLK — Master Clock
The rising edge of CLK strobes all
enabled registers.
CCCLK — Coefficient/Control Clock
When LD is LOW, the rising edge of
CCCLK latches data on CC
11-0
into the
device.
Inputs
D1
11-0
– D4
11-0
— Data Input
D1–D4 are the 12-bit registered data
input ports. Data is latched on the
rising edge of CLK.
A
7-0
— Row Address
A
7-0
determines which row in the
coefficient banks feed data to the
multipliers. A
7-0
is latched on the
rising edge of CLK. When a new
row address is loaded into the row
address register, data from the
coefficient banks will be latched into
the multiplier input registers on the
next rising edge of CLK.
2
2
–9
1 0
2
–10
2
–11
11 10 9
–2
0
2
–1
2
–2
(Sign)
2 1 0
2
–9
2
–10
2
–11
Integer Two's Complement
11 10 9
–2
11
2
10
2
9
(Sign)
2 1 0
2
2
2
1
2
0
11 10 9
–2
11
2
10
2
9
(Sign)
2 1 0
2
2
2
1
2
0
T
ABLE
1. O
UTPUT
F
ORMATS
SHIFT
4-0
00000
00001
00010
S
15
S
14
S
13
F
15
F
14
F
13
F
16
F
15
F
14
F
17
F
16
F
15
···
···
···
···
S
8
F
8
F
9
F
10
S
7
F
7
F
8
F
9
···
···
···
···
S
2
F
2
F
3
F
4
S
1
F
1
F
2
F
3
S
0
F
0
F
1
F
2
·
·
·
01110
01111
10000
·
·
·
·
·
·
·
·
·
···
···
···
·
·
·
·
·
·
···
···
···
·
·
·
·
·
·
·
·
·
F
29
F
28
F
27
F
30
F
29
F
28
F
31
F
30
F
29
F
22
F
21
F
23
F
22
F
24
F
23
F
16
F
15
F
14
F
17
F
16
F
15
F
18
F
17
F
16
CC
11-0
— Control/Coefficient Data Input
CC
11-0
is used to load data into the
coefficient banks and control regis-
ters. Data present on
CC
11-0
is
latched on the rising edge of CCCLK
when LD is LOW.
Outputs
S
15-0
— Data Output
S
15-0
is the 16-bit registered data
output port.
Controls
ENB
1
–ENB
4
— Data Input Enables
The ENB
N
(
N
= 1, 2, 3, or 4) inputs
allow the D
N
registers to be updated
on each clock cycle. When ENB
N
is
LOW, data on D
N11-0
is latched into
the D
N
register on the rising edge of
CLK. When ENB
N
is HIGH, data on
D
N11-0
is not latched into the D
N
register and the register contents
will not be changed.
ENBA — Row Address Input Enable
The ENBA input allows the row
address register to be updated on
each clock cycle. When ENBA is
LOW, data on A
7-0
is latched into
the row address register on the rising
edge of CLK. When ENBA is HIGH,
data on A
7-0
is not latched into the
row address register and the register
contents will not be changed.
OE — Output Enable
When OE is LOW, S
15-0
is enabled for
output. When OE is HIGH, S
15-0
is
placed in a high-impedance state.
Video Imaging Products
2
08/16/2000–LDS.3347-G
LF3347
DEVICES INCORPORATED
High-Speed Image Filter with Coefficient RAM
T
ABLE
2. R
EGISTER
F
ORMATS
Register
CS0
CS1
CS255
RND0
RND1
RND15
LMT0
LMT1
LMT15
Load Address
000H
001H
0FFH
800H
801H
80FH
C00H
C01H
C0FH
Bits
11-0
11-0
11-0
31-0
31-0
31-0
31-16/15-0
31-16/15-0
Register Description
Coefficient Set 0
Coefficient Set 1
Coefficient Set 255
Rounding Register 0
Rounding Register 1
Rounding Register 15
Upper / Lower Limit Register 0
Upper / Lower Limit Register 0
A
7-0
00H
01H
FFH
0000
0001
1111
0000
0001
1111
SELRND
3-0
SELLMT
3-0
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
31-16/15-0 Upper / Lower Limit Register 15
power up to ensure proper operation of
the input circuitry.
It takes five CCCLK clock cycles to load
one coefficient set into the four coefficient
banks or to load one control register.
When the input circuitry is enabled (LD
goes LOW), the first value loaded into the
device on CC
11-0
is an address which
determines what will be loaded (see
Table 2). The next four values loaded on
CC
11-0
is the data to be loaded into the
coefficient banks or control register (see
Tables 3-5). After the last data value is
loaded, another coefficient bank address
or control register may be loaded by
feeding another address into CC
11-0
.
When all desired coefficient banks and
control registers are loaded, the input
circuitry must be disabled by setting LD HIGH.
SELRND
3-0
— Round Select
SELRND
3-0
allows the user to select
which rounding register will be used
in the rounding circuit to round/offset
the data.
SHIFT
4-0
— Shift
SHIFT
4-0
determines which 16-bits of
the 32-bits from the accumulator are
passed to the output (see Table 1).
·
·
·
·
·
·
·
·
·
OCEN — Output Clock Enable
When OCEN is LOW, the output
register is enabled for data loading.
When OCEN is HIGH, output register
loading is disabled and the register’s
contents will not change.
ACC — Accumulator Control
The ACC input determines whether
internal accumulation is performed. If
ACC is LOW, no accumulation is
performed, the prior accumulated sum
is cleared, and the current sum of
products is output. When ACC is
HIGH, the emerging product is added
to the sum of the previous products.
LD — Load Control
LD enables the loading of data into the
coefficient banks and control registers
(control registers are the round and limit
registers). When LD is LOW, data on
CC
11-0
is latched into the device on the
rising edge of CCCLK. When LD is
HIGH, data cannot be loaded into the
coefficient banks and control registers.
When enabling the input circuitry for
data loading, the LF3347 requires a
HIGH to LOW transition of LD in order
to function properly. Therefore, LD
needs to be set HIGH immediately after
F
IGURE
2. R
OUNDING
, S
ELECTING
,
L
IMITING
C
IRCUITRY
32
RND
31-0
RND
32
32
SHIFT
4-0
SELECT
16
16
ULMT
15-0
LLMT
15-0
LIMIT
16
LMTEN
SELLMT
3-0
— Limit Select
SELLMT
3-0
allows the user to control
which limiting register will be used in
the limiting circuit to set the upper
and lower limits on the data.
LMTEN — Limit Enable
When LMTEN is LOW, limiting is
enabled and the selected limit register
is used to determine the valid range of
output values for the overall filter.
When HIGH, limiting is disabled.
Video Imaging Products
3
08/16/2000–LDS.3347-G
LF3347
DEVICES INCORPORATED
High-Speed Image Filter with Coefficient RAM
registers. Each limit register contains both
an upper and lower limit value. The
lower limit is stored in bits 15-0 and the
upper limit is stored in bits 31-16. If the
value fed to the limiting circuitry is less
than the lower limit, the lower limit is
passed to the device output. If the value
fed to the limiting circuitry is greater than
the upper limit, the upper limit is passed
to the device output. When loading limit
values into the device, the upper limit must
be greater than the lower limit. In the
example shown in Table 4, limit register
15 is loaded with a lower limit of 0123H
and an upper limit of 7FEDH. A limit
register is not written to until all four data
values have been loaded into the device.
SELLMT
3-0
determines which limit
register is used for limiting. A value of 0
on SELLMT
3-0
selects limit register 0. A
value of 1 selects limit register 1 and so on.
FUNCTIONAL DESCRIPTION
Coefficient Banks
The LF3347 has four coefficient banks
which feed coefficient values to the
multipliers. Each bank can store 256
12-bit coefficients. In the example
shown in Table 3, address 10 in coeffi-
cient banks 1 through 4 is loaded with
the following values: ABCH, 789H,
456H, 123H. The coefficient banks are
not written to until all four coefficients
have been loaded into the device.
A
7-0
determines which coefficient set is
sent to the multipliers. A value of 0 on
A
7-0
selects set 0. A value of 1 selects
set 1 and so on.
Rounding/Offset
The accumulator output may be rounded
before being sent to the output select
section. Rounding is user-selectable and
is accomplished by adding the contents of
a round register to the accumulator
output (see Figure 2). There are sixteen
32-bit round registers. In the example in
Table 4, round register 10 is loaded with
76543210H. A round register is not
written to until all four data values have
been loaded into the device.
SELRND
3-0
determines which round
register is used for rounding. A value of 0
on SELRND
3-0
selects round register 0. A
value of 1 selects round register 1 and so
on. If rounding is not desired, a round
register should be loaded with 0 and
selected as the register for rounding.
Output Select
The filter output word width is 32-bits.
However, only 16-bits may be sent to the
device output. SHIFT4-0 determines
which 16 bits are passed to the device
output (See Table 1).
Output Limiting
An output limiting function is provided
for the output of the filter. When limiting is
enabled (LMTEN LOW), the limit register
selected with SELLMT
3-0
determines the
valid range of output values for the overall
filter. There are sixteen 32-bit limit
T
ABLE
3.
1st Word
Address
2nd Word
Bank 1
3rd Word
Bank 2
4th Word
Bank 3
5th Word
Bank 4
C
OEFFICIENT
B
ANK
L
OADING
F
ORMAT
CC
11
CC
10
CC
9
CC
8
CC
7
CC
6
CC
5
CC
4
CC
3
CC
2
CC
1
CC
0
0
1
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
1
0
0
0
0
0
1
0
0
1
0
0
1
0
1
0
1
0
1
1
1
0
0
0
1
0
1
0
1
0
0
1
1
0
0
1
0
1
T
ABLE
4.
1st Word
Address
2nd Word
3rd Word
4th Word
5th Word
R
OUND
R
EGISTER
L
OADING
F
ORMAT
CC
11
CC
10
CC
9
CC
8
CC
7
CC
6
CC
5
CC
4
CC
3
CC
2
CC
1
CC
0
1
R
R
R
R
0
R
R
R
R
0
R
R
R
R
0
R
R
R
R
0
0
0
0
**0
0
0
0
1
1
0
0
1
0
1
0
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
0
1
0
1
0
*0
0
0
0
R = Reserved. Must be set to “0”.
* This bit represents the LSB of the Round Register.
** This bit represents the MSB of the Round Register.
T
ABLE
5.
1st Word
Address
2nd Word
3rd Word
4th Word
5th Word
L
IMIT
R
EGISTER
L
OADING
F
ORMAT
CC
11
CC
10
CC
9
CC
8
CC
7
CC
6
CC
5
CC
4
CC
3
CC
2
CC
1
CC
0
1
R
R
R
R
1
R
R
R
R
0
R
R
R
R
0
R
R
R
R
0
0
*0
1
**0
0
0
0
1
1
0
1
0
1
1
0
0
0
0
1
1
0
0
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
1
1
R = Reserved. Must be set to “0”.
* This bit represents the MSB of the Lower Limit Register.
** This bit represents the MSB of Upper Limit Register.
Video Imaging Products
4
08/16/2000–LDS.3347-G
LF3347
DEVICES INCORPORATED
High-Speed Image Filter with Coefficient RAM
M
AXIMUM
R
ATINGS
Above which useful life may be impaired (Notes 1, 2, 3, 8)
Storage temperature ........................................................................................................... –65°C to +150°C
Operating ambient temperature ........................................................................................... –55°C to +125°C
V
CC
supply voltage with respect to ground ............................................................................ –0.5 V to +4.5 V
Input signal with respect to ground .......................................................................................... –0.5 V to 5.5 V
Signal applied to high impedance output ................................................................................. –0.5 V to 5.5 V
Output current into low outputs ............................................................................................................. 25 mA
Latchup current ............................................................................................................................... > 400 mA
ESD Classification (MIL-STD-883E METHOD 3015.7) ...................................................................... Class 3
O
PERATING
C
ONDITIONS
To meet specified electrical and switching characteristics
Mode
Active Operation, Commercial
Active Operation, Military
Temperature Range
(Ambient)
0°C to +70°C
–55°C to +125°C
Supply
Voltage
3.00 V
≤
V
CC
≤
3.60 V
3.00 V
≤
V
CC
≤
3.60 V
E
LECTRICAL
C
HARACTERISTICS
Over Operating Conditions (Note 4)
Symbol
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC1
I
CC2
C
IN
C
OUT
Parameter
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Input Current
Output Leakage Current
V
CC
Current, Dynamic
V
CC
Current, Quiescent
Input Capacitance
Output Capacitance
(Note 3)
Test Condition
V
CC
= Min.,
I
OH
= –4 mA
V
CC
= Min.,
I
OL
= 8.0 mA
Min
2.4
Typ
Max
Unit
V
0.4
2.0
0.0
V
CC
0.8
±10
±10
150
2
10
10
V
V
V
µA
µA
mA
mA
pF
pF
Ground
≤
V
IN
≤
V
CC
(Note 12)
Ground
≤
V
OUT
≤
V
CC
(Note 12)
(Notes 5, 6)
(Note 7)
T
A
= 25°C, f = 1 MHz
T
A
= 25°C, f = 1 MHz
Video Imaging Products
5
08/16/2000–LDS.3347-G
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