256K x 8
Radiation Hardened
Static RAM MCM – 5 V
Features
201A072
225A837
Product Description
Other
• Read/Write Cycle Times
≤
30 ns (-55°C to 125°C)
• SMD Number 5962H99541
• Asynchronous Operation
• CMOS or TTL Compatible I/O
• Single 5 V ±10% Power Supply
• Low Operating Power
• Packaging Options
• 40-Lead Dual Flat Pack (0.855” x 0.710”)
Radiation
• Fabricated with Bulk CMOS 0.5 µm Process
• Total Dose Hardness through 1x10
6
rad(Si)
• Neutron Hardness through 1x10
14
N/cm
2
• Dynamic and Static Transient Upset Hardness
through 1x10
9
rad(Si)/s
• Soft Error Rate of < 1x10
-11
Upsets/Bit-Day
• Dose Rate Survivability through 1x10
12
rad(Si)/s
• Latchup Free
General Description
The 256K x 8 radiation hardened static RAM is
composed of two 128K x 8 SRAM memory die
assembled in a single, double-sided ceramic
substrate. Each die is a high performance
131,072 word x 8-bit static random access
memory with industry-standard functionality. It
is fabricated with BAE SYSTEMS’ radiation
hardened technology and is designed for use in
systems operating in radiation environments.
The RAM operates over the full military
temperature range and requires a single 5 V
±10% power supply. The RAM is available with
either TTL or CMOS compatible I/O. Power
consumption is typically less than 40 mW/MHz
in operation, and less than 20 mW in the low
power disabled mode. The RAM read operation
is fully asynchronous, with an associated
typical access time of 19 nanoseconds.
BAE SYSTEMS’ enhanced bulk CMOS
technology is radiation hardened through the
use of advanced and proprietary design, layout,
and process hardening techniques.
BAE SYSTEMS • 9300 Wellington Road • Manassas, Virginia 20110-4122
Functional Diagram for Top and Bottom SRAMs
A0
Top/Bottom Decoder
Note:
1) All package leads are common for
top and bottom SRAM devices
except S1 for bottom SRAM and
S2 for top SRAM.
A1 - A2
Block Address Decoder
A3
L/R Side/Block
((256 x 32) x 2 x 4) x 8 x 2
Memory Cell Array
A9 - A16
Row Address Decoder
8 Bit Word Input/Output
W
Column Address Decoder
G
E
S1; S2
DQ0-DQ7
A4-A8
Signal Definitions
A: 0-16
– Address input pins that select a particular
eight-bit word within the memory array.
– Bi-directional data pins that serve as data
outputs during a read operation and as data
inputs during a write operation.
– Negative chip select, when at a low level,
allows normal read or write operation. When at
a high level, S1 or S2 forces the SRAM to a
precharge condition, holds the data output
drivers in a high impedance state and disables
the data input buffers only. If this signal is not
used, it must be connected to GND.
W
DQ: 0-7
– Negative write enable, when at a low level, activates a
write operation and holds the data output drivers in a
high impedance state. When at a high level, W allows
normal read operation.
– Negative output enable, when at a high level holds the
data output drivers in a high impedance state. When at
a low level, the data output driver state is defined by S1
or S2, W, and E. If this signal is not used it must be
connected to GND.
– Chip enable, when at a high level allows normal
operation. When at a low level, E forces the SRAM to a
precharge condition, holds the data output drivers in a
high impedance state and disables all the input buffers
except the S1 or S2 input buffer. If this signal is not
used, it must be connected to V
DD
.
G
S1
(Bottom)
S2
(Top)
E
Truth Table
Mode
Write1
Read1
Write2
Read2
Standby
Standby
(3)
Inputs
(1),(2)
S1
Low
Low
High
High
X
High
S2
High
High
Low
Low
X
High
E
High
High
High
High
Low
X
W
Low
High
Low
High
X
X
G
X
Low
X
Low
X
X
I/O
Data-In
Data-Out
Data-In
Data-Out
High-Z
High-Z
2
Power
Active
Active
Active
Active
Standby
Standby
Notes:
1) V
IN
for don’t care (X) inputs = V
IL
or V
IH
.
2) When G = high, I/O is high-Z.
3) To dissipate the minimum amount of
standby power when in standby mode:
S1 = S2 = V
DD
. All other input levels may
float.
Absolute Maximum Ratings
Applied Conditions
(1)
Minimum
Maximum
Storage Temperature Range (Ambient)
Operating Temperature Range (T
case
)
Positive Supply Voltage
Input Voltage
(2)
Output Voltage
(2)
Power Dissipation
(3)
Lead Temperature (Soldering 5 sec)
Electrostatic Discharge Sensitivity
(4)
Notes:
-70°C
-55°C
-0.5 V
-0.5 V
-0.5 V
+150°C
+125°C
+7.0 V
V
DD
+ 0.5 V
V
DD
+ 0.5 V
2.0 W
+250°C
(Class II)
1) Stresses above the absolute maximum rating may cause permanent
damage to the device. Extended operation at the maximum levels may
degrade performance and affect reliability. All voltages are with
reference to the module ground leads.
2) Maximum applied voltage shall not exceed +7.0 V.
3) Guaranteed by design; not tested.
4) Class as defined in MIL-STD-883, Method 3015.
Recommended Operating Conditions
Symbol
Parameters
(1)
Minimum
Maximum
Units
V
DD
GND
T
C
V
IL
V
IH
Supply Voltage
Supply Voltage Reference
Case Temperature
Input Logic “Low” - CMOS
Input Logic “Low” - TTL
Input Logic “High” - CMOS
Input Logic “High” - TTL
Note:
+4.5
0.0
-55
-0.3
0.0
+3.5
+2.0
+5.5
0.0
+125
+1.5
+0.8
V
DD
V
DD
Volt
Volt
Celsius
Volt
Volt
1)All voltages referenced to GND.
Power Sequencing
Power shall be applied to the device only in the following
sequences to prevent damage due to excessive currents:
• Power-Up Sequence: GND, V
DD
, Inputs
• Power-Down Sequence: Inputs, V
DD
, GND
3
DC Electrical Characteristics
Limits
Minimum
Maximum
182
186
4.0
8.0
4.0
8.0
2.0
4.0
4.0
V
DD
- 0.5 V
0.5
0.05
2.5
3.5
2.0
1.5
0.8
-10
0
10
20
20
30
20
30
Test
Symbol
Test Conditions
(1)
Device Type
Units
Supply Current
(Cycling Selected)
I
DD1
F = F
MAX
= 1/t
AVAV(min)
All (Except
S2 = V
DD
and S1 = GND) or
Engineering Level)
S1 = V
DD
and S2 = GND)
E = V
DD
Engineering Level
No Output Load
F = F
MAX
= 1/t
AVAV(min)
S1 = S2 = V
DD
E = GND
F = 0 MHz
S1 = S2 = V
DD
E = GND
All (Except
Engineering Level)
Engineering Level
All (Except
Engineering Level)
Engineering Level
All (Except
Engineering Level)
Engineering Level
mA
mA
mA
mA
mA
mA
mA
mA
V
V
V
V
V
µA
µA
pF
pF
pF
pF
Supply Current
(Cycling De-Selected)
Supply Current
(Standby)
I
DD2
I
DD3
Data Retention Current
I
DR
V
DD
= 2.5 V
I
OH
= -4 mA
I
OH
= -200 µA
I
OL
= 8 mA
I
OL
= 200 µA
V
DD
= V
DR
High Level Output Voltage
Low Level Output Voltage
Data Retention Voltage
High Level Input Voltage
Low Level Input Voltage
Input Leakage
Output Leakage
V
OH
V
OL
V
DR (2)
V
IH
V
IL
I
ILK
I
OLK
All
All
All
CMOS
TTL
CMOS
TTL
0 V
≤
V
IN
≤
5.5 V
0 V
≤
V
OUT
≤
5.5 V
By Design/
Verified By
Characterization
By Design/
Verified By
Characterization
All
All
All CMOS (Except
Engineering Level)
CMOS Engineering
Level + TTL
All CMOS (Except
Engineering Level)
CMOS Engineering
Level + TTL
C
in
(3)
C
out
(3)
Notes:
1) Typical operating conditions: -55°C
≤
T
case
≤
+125°C; 4.5 V
≤
V
DD
≤
5.5 V; unless otherwise specified.
2) S1 or S2 high, W high, or E low must occur while address transitions.
3) Guaranteed by design and verified by periodic characterization.
Output Load Circuit
300
Ω
± 10%
2.8V
50 pF ± 10%
4
Read Cycle AC Timing Characteristics
(1)
Minimum or
Maximum
Minimum
Test
Symbol
Device Type
X3X CMOS, TTL
X41, 2, 4 - 7 CMOS, X43 TTL
X43 CMOS
X3X CMOS, TTL
X41, 2, 4 - 7 CMOS, X43 TTL
X43 CMOS
X3X CMOS, TTL
X41, 2, 4 - 7 CMOS, X43 TTL
X43 CMOS
X3X CMOS, TTL
X41, 2, 4 - 7 CMOS, X43 TTL
X43 CMOS
X3X
X4X
All
All
All
All
X3X
X4X
X3X
X4X
X3X
X4X
X3X
X4X
X3X
X4X
Limits Units
30
40
45
30
40
45
30
40
45
30
40
45
12
15
0
0
0
0
12
15
12
15
12
15
12
15
12
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
t
AVAV (2)
Address Access Time
t
AVQV
Maximum
Chip Select Access Time
t
SLQV
Maximum
Chip Enable Access Time
t
EHQV
Maximum
Output Enable Access Time
Chip Select to Output Active
Chip Enable to Output Active
Output Enable to Output Active
Output Hold After Address Change
Chip Select to Output Disable
Chip Disable to Output Disable
Output Enable to Output Disable
Chip Select1 to Chip Select2
(3)
Chip Select2 to Chip Select1
(3)
t
GLQV
t
SLQX
t
EHQX
t
GLQX
t
AHQX
t
SHQZ
t
ELQZ
t
GHQZ
t
S1HS2L
t
S2HS1L
Maximum
Minimum
Minimum
Minimum
Minimum
Maximum
Maximum
Maximum
Minimum
Minimum
Notes:
1) Test conditions: input switching levels V
IL
/V
IH
= 0.5 V/V
DD
- 0.5 V (CMOS), V
IL
/V
IH
= 0 V/3 V (TTL), input rise
and fall times < 5 ns, input and output timing reference levels shown in the Tester AC Timing Characteristics
table, capacitive output loading = 50 pF. For C
L
= 50 pF, derate access times by 0.02 ns/pF (typical).
-55°C
≤
T
case
≤
+125°C; 4.5 V
≤
V
DD
≤
5.5 V; unless otherwise specified.
2) Cycle time per individual die.
3) Parameter is guaranteed but not tested. Parameter is the sum of t
SLQX
and t
SHQZ
; both of these parameters
are tested.
5
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