LF9502
DEVICES INCORPORATED
2K Programmable Line Buffer
LF9502
DEVICES INCORPORATED
2K Programmable Line Buffer
DESCRIPTION
The
LF9502
is a high-speed, 10-bit
programmable line buffer. Some
applications the LF9502 is useful for
include sample rate conversion, data
time compression/expansion, soft-
ware controlled data alignment, and
programmable serial data shifting. By
using the MODSEL pin, two different
modes of operation can be selected:
delay mode and data recirculation
mode. The delay mode provides a
minimum of 2 to a maximum of 2049
clock cycles of delay between the
input and output of the device. The
data recirculation mode provides a
feedback path from the data output to
the data input for use as a program-
mable circular buffer.
By using the length control input
(LC
10-0
) and the length control enable
(LCEN) the length of the delay buffer
or amount of recirculation delay can
be programmed. Providing a delay
value on the LC
10-0
inputs and driving
LCEN LOW will load the delay value
into the length control register on the
next selected clock edge. Two regis-
ters, one preceeding the program-
mable delay RAM and one following,
are included in the delay path. There-
fore, the programmed delay value
should equal the desired delay minus
2. This consequently means that the
value loaded into the length control
register must range from 0 to 2047 (to
provide an overall range of 2 to 2049).
The active edge of the clock input,
either positive or negative edge, can
be selected with the clock select
(CLKSEL) input. All timing is based
on the active clock edge selected by
CLKSEL. Data can be held tempo-
rarily by using the clock enable
(CLKEN) input.
FEATURES
u
50 MHz Maximum Operating
Frequency
u
Programmable Buffer Length from
2 to 2049 Clock Cycles
u
10-bit Data Inputs and Outputs
u
Data Delay and Data Recirculation
Modes
u
Supports Positive or Negative Edge
System Clocks
u
Expandable Data Word Width or
Buffer Length
u
44-pin PLCC, J-Lead
LF9502 B
LOCK
D
IAGRAM
MODSEL
LCO
10-0
11
LCEN
REGISTER
REGISTER
11
PROGRAMMABLE
2K DELAY RAM
REGISTER
DI
9-0
10
10
10
REGISTER
10
OE
10
10
MUX
DO
9-0
10
CLKSEL
CLKEN
CLK
CLOCK
GENERATOR
TO ALL REGISTERS
Video Imaging Products
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08/16/2000–LDS.9502-G
LF9502
DEVICES INCORPORATED
2K Programmable Line Buffer
Outputs
DO
9-0
— Data Output
The 10-bit data output appears on
DO
9-0
on the Nth clock cycle, where N
is the overall delay (desired delay).
Controls
LCEN — Length Control Enable
When LCEN is driven LOW, the next
active clock edge will cause the
loading of the delay value present at
the LC
10-0
input.
OE — Output Enable
The Output Enable controls the state
of DO
9-0
. Driving OE LOW enables
the output port. When OE is HIGH,
DO
9-0
is placed in a high-impedance
state. The internal transfer of data is
not affected by this control.
MODSEL — Mode Select
The Mode Select pin is used to choose
the desired mode of operation: data
delay mode or data recirculation
mode. Driving MODSEL LOW places
the device in the delay mode. The
device operates as a programmable
pipeline register. New data from the
DI
9-0
input is loaded on every active
edge of CLK. Driving MODSEL
HIGH places the device in the data
recirculation mode. The device
operates as a programmable circular
buffer. The output of the device is
routed back to the input. MODSEL
may be changed during device
operation (synchronously), however,
the required setup and hold times,
with respect to CLK, must be met.
CLKSEL — Clock Select
The CLKSEL control allows the
selection of the active edge of CLK. A
LOW on CLKSEL selects negative-
edge triggering of the device. Driving
CLKSEL HIGH selects positive-edge
triggering. All timing specifications
are referrenced to the selected active
edge of CLK.
CLKEN — Clock Enable
The Clock Enable control enables and
disables the CLK input. Driving
CLKEN LOW enables CLK and causes
the device to operate in a normal
fashion. When CLKEN is HIGH, CLK
is disabled and the device will hold all
internal operations and data. CLKEN
may be changed during device
operation (synchronously), however,
the required setup and hold times,
with respect to CLK, must be met.
The changing of CLKEN takes effect
on the active edge of CLK following
the edge in which it was latched.
SIGNAL DEFINITIONS
Power
V
CC
and GND
+5 V power supply. All pins must be
connected.
Clock
CLK — Master Clock
The active edge of CLK, selected by
CLKSEL, strobes all registers. All
timing specifications are referenced to
the active edge of CLK.
Inputs
DI
9-0
— Data Input
10-bit data, from the data input, is
latched into the device on the active
edge of CLK when MODSEL is LOW.
LC
10-0
— Length Control Input
The 11-bit value is used to specify the
length of the delay buffer, between
DI
9-0
and DO
9-0
, or the amount of
recirculation delay. An integer value
ranging from 0 to 2047 is used to
select a delay ranging from 2 to 2049
clock cycles. The value placed on the
LC
10-0
inputs is equal to the desired
delay minus 2. The data presented on
LC
10-0
is loaded into the device on the
active edge of CLK, selected by
CLKSEL, in conjunction with LCEN
being driven LOW.
Video Imaging Products
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08/16/2000–LDS.9502-G
LF9502
DEVICES INCORPORATED
2K Programmable Line Buffer
M
AXIMUM
R
ATINGS
Above which useful life may be impaired (Notes 1, 2, 3, 8)
Storage temperature ........................................................................................................... –65°C to +150°C
Operating ambient temperature ........................................................................................... –55°C to +125°C
V
CC
supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V
Input signal with respect to ground ............................................................................... –0.5 V to V
CC
+ 0.5 V
Signal applied to high impedance output ...................................................................... –0.5 V to V
CC
+ 0.5 V
Output current into low outputs ............................................................................................................. 25 mA
Latchup current ............................................................................................................................... > 400 mA
O
PERATING
C
ONDITIONS
To meet specified electrical and switching characteristics
Mode
Active Operation, Commercial
Temperature Range
(Ambient)
0°C to +70°C
Supply Voltage
4.75 V
≤
V
CC
≤
5.25 V
E
LECTRICAL
C
HARACTERISTICS
Over Operating Conditions (Note 4)
Symbol
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC1
I
CC2
C
IN
C
OUT
Parameter
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Input Current
Output Leakage Current
V
CC
Current, Dynamic
V
CC
Current, Quiescent
Input Capacitance
Output Capacitance
(Note 3)
Test Condition
V
CC
= Min.,
I
OH
= –4.0 mA
V
CC
= Min.,
I
OL
= 4.0 mA
Min
2.4
Typ
Max
Unit
V
0.4
2.0
0.0
V
CC
0.8
±10
±10
125
500
10
10
V
V
V
µA
µA
mA
µA
pF
pF
Ground
≤
V
IN
≤
V
CC
(Note 12)
Ground
≤
V
OUT
≤
V
CC
(Note 12)
(Notes 5, 6)
(Note 7)
T
A
= 25°C, f = 1 MHz
T
A
= 25°C, f = 1 MHz
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ISCONTINUED
S
PEED
G
RADE
Symbol
DEVICES INCORPORATED
C
OMMERCIAL
O
PERATING
R
ANGE
(0°C to +70°C)
Notes 9, 10 (ns)
SWITCHING CHARACTERISTICS
2K Programmable Line Buffer
LF9502–
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0
5
0
4
0
5
6
5
5
5
0
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12
40
13
15
12
12
13
2
2
4
2
2
2
40*
22
25
25
10
31
10
12
10
10
10
2
2
4
2
2
2
31*
16
24
24
*When CLKSEL is HIGH, assume CLK is inverted.
F
UNCTIONAL
T
IMING
— CLKSEL LOW
t
DIS
t
ENA
t
OH
t
OUT
t
MH
t
MS
t
LEH
t
LES
t
LH
t
LS
t
EH
t
ES
t
DH
t
DS
t
PW
t
CYC
MODSEL
Parameter
Three-State Output Disable Delay
(Note 11)
Three-State Output Enable Delay
(Note 11)
Output Hold Time
(Note 8)
Clock to Data Out
Mode Select Hold Time
Mode Select Setup Time
Length Control Enable to Clock Hold Time
Length Control Enable to Clock Setup Time
Length Control Input Hold Time
Length Control Input Setup Time
Clock Enable to Clock Hold Time
Clock Enable to Clock Setup Time
Data Input Hold Time
Data Input Setup Time
Clock Pulse Width
Cycle Time
DO
9-0
CLK*
DI
9-0
OE
t
MS
t
PW
t
DS
t
OH
t
CYC
t
OUT
t
PW
t
DH
t
DIS
4
HIGH IMPEDANCE
Min Max Min Max Min Max Min Max Min Max
Video Imaging Products
t
ENA
t
MH
25
10
2
8
2
4
2
8
8
8
8
2
2
15
15
15
20
2
6
2
4
2
6
8
6
6
6
2
2
20
08/16/2000–LDS.9502-G
14
14
14
LF9502
432109876543210987654321
432109876543210987654321
432109876543210987654321
*D
ISCONTINUED
S
PEED
G
RADE
Symbol
DEVICES INCORPORATED
C
OMMERCIAL
O
PERATING
R
ANGE
(0°C to +70°C)
Notes 9, 10 (ns)
SWITCHING CHARACTERISTICS
2K Programmable Line Buffer
LF9502–
25
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15
0
5
0
4
0
5
6
5
5
5
0
0
15*
10
12
12
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12
40
13
15
13
12
13
2
2
4
2
2
2
40*
22
25
25
10
31
10
12
10
10
10
2
2
4
2
2
2
31*
16
24
20
*When CLKSEL is HIGH, assume CLK is inverted.
L
ENGTH
C
ONTROL
T
IMING
— CLKSEL LOW
C
LOCK
E
NABLE
T
IMING
— CLKSEL LOW
t
DIS
t
ENA
t
OH
t
OUT
t
MH
t
MS
t
LEH
t
LES
t
LH
t
LS
t
EH
t
ES
t
DH
t
DS
t
PW
t
CYC
INTERNAL
CLOCK
Parameter
Three-State Output Disable Delay
(Note 11)
Three-State Output Enable Delay
(Note 11)
Output Hold Time
(Note 8)
Clock to Data Out
Mode Select Hold Time
Mode Select Setup Time
Length Control Enable to Clock Hold Time
Length Control Enable to Clock Setup Time
Length Control Input Hold Time
Length Control Input Setup Time
Clock Enable to Clock Hold Time
Clock Enable to Clock Setup Time
Data Input Hold Time
Data Input Setup Time
Clock Pulse Width
Cycle Time
LC
10-0
LCEN
CLK*
CLKEN
CLK*
t
LES
t
LS
t
ES
t
LEH
t
LH
t
PW
5
t
ES
Min Max Min Max Min Max Min Max Min Max
Video Imaging Products
t
MH
t
MH
25
10
2
8
2
4
2
8
8
8
8
2
2
15
15
15
20
2
6
2
4
2
6
8
6
6
6
2
2
20
08/16/2000–LDS.9502-G
14
14
14
LF9502
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