LatticeECP/EC Family Data Sheet
Version 01.3
LatticeECP/EC Family Data S
Introdu
November 2004
Preliminary
Features
■
Extensive Density and Package Options
• 1.5K to 41K LUT4s
• 65 to 576 I/Os
• Density migration supported
−
−
−
−
−
−
LVCMOS 3.3/2.5/1.8/1.5/1.2
LVTTL
SSTL 3/2 Class I, II, SSTL18 Cla
HSTL 18 Class I, II, III, HSTL15
PCI
LVDS, Bus-LVDS, LVPECL, RSD
■
sysDSP™ Block (LatticeECP™ Versions)
• High performance multiply and accumulate
• 4 to 10 blocks
−
4 to 10 36x36 multipliers or
– 16 to 40 18x18 multipliers or
−
32 to 80 9x9 multipliers
■
Dedicated DDR Memory Support
• Implements interface up to DDR400
■
sysCLOCK™ PLLs
• Up to 4 analog PLLs per device
• Clock multiply, divide and phase shift
■
Embedded and Distributed Memory
• 18 Kbits to 645 Kbits sysMEM™ Embedded
Block RAM (EBR)
• Up to 163 Kbits distributed RAM
• Flexible memory resources:
−
Distributed and block memory
■
System Level Support
• IEEE Standard 1149.1 Boundary Sca
ispTRACY™ internal logic analyzer c
• SPI boot flash interface
• 1.2V power supply
■
Low Cost FPGA
■
Flexible I/O Buffer
• Programmable sysIO™ buffer supports wide
range of interfaces:
Table 1-1. LatticeECP/EC Family Selection Guide
Device
PFU/PFF Rows
PFU/PFF Columns
PFUs/PFFs
LUTs (K)
Distributed RAM (Kbits)
EBR SRAM (Kbits)
EBR SRAM Blocks
sysDSP Blocks
1
• Features optimized for mainstream a
• Low cost TQFP and PQFP packaging
LFEC1
12
16
192
1.5
6
18
2
—
—
1.2
2
67
97
112
LFEC3
16
24
384
3.1
12
55
6
—
—
1.2
2
67
97
145
160
LFEC6/
LFECP6
24
32
768
6.1
25
92
10
4
16
1.2
2
LFEC10/ LFEC15/ LFEC20/ LFEC33/
LFECP10 LFECP15 LFECP20 LFECP33
32
40
1280
10.2
41
277
30
5
20
1.2
4
40
48
1920
15.4
61
350
38
6
24
1.2
4
44
56
2464
19.7
79
424
46
7
28
1.2
4
64
64
4096
32.8
131
535
58
8
32
1.2
4
18x18 Multipliers
1
V
CC
Voltage (V)
Number of PLLs
Packages and I/O Combinations:
100-pin TQFP (14 x 14 mm)
144-pin TQFP (20 x 20 mm)
208-pin PQFP (28 x 28 mm)
256-ball fpBGA (17 x 17 mm)
484-ball fpBGA (23 x 23 mm)
672-ball fpBGA (27 x 27 mm)
900-ball fpBGA (31 x 31 mm)
1. LatticeECP devices only.
97
147
195
224
147
195
288
195
352
360
400
360
496
© 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/lega
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change
www.latticesemi.com
1-1
Intro
Lattice Semiconductor
Intr
LatticeECP/EC Family Da
Introduction
The LatticeECP/EC family of FPGA devices has been optimized to deliver mainstream FPGA features
For maximum performance and value, the LatticeECP (EConomy Plus) FPGA concept combines an effi
fabric with high-speed dedicated functions. Lattice’s first family to implement this approach is the Lattic
(EConomy Plus DSP) family, providing dedicated high-performance DSP blocks on-chip. The LatticeE
omy) family supports all the general purpose features of LatticeECP devices without dedicated functio
achieve lower cost solutions.
The LatticeECP/EC FPGA fabric, which was designed from the outset with low cost in mind, contains a
FPGA elements: LUT-based logic, distributed and embedded memory, PLLs and support for mains
Dedicated DDR memory interface logic is also included to support this memory that is becoming increa
alent in cost-sensitive applications.
The ispLEVER
®
design tool from Lattice allows large complex designs to be efficiently implemented usi
ceECP/EC family of FPGA devices. Synthesis library support for LatticeECP/EC is available for popula
thesis tools. The ispLEVER tool uses the synthesis tool output along with the constraints from its flo
tools to place and route the design in the LatticeECP/EC device. The ispLEVER tool extracts the timi
routing and back-annotates it into the design for timing verification.
Lattice provides many pre-designed IP (Intellectual Property) ispLeverCORE™ modules for the Lat
family. By using these IPs as standardized blocks, designers are free to concentrate on the unique asp
design, increasing their productivity.
1-2
LatticeECP/EC Family Data S
Archite
November 2004
Preliminary
Architecture Overview
The LatticeECP™-DSP and LatticeEC™ architectures contain an array of logic blocks surrounded by P
ble I/O Cells (PIC). Interspersed between the rows of logic blocks are rows of sysMEM Embedded
(EBR) as shown in Figures 2-1 and 2-2. In addition, LatticeECP-DSP supports an additional row of DS
shown in Figure 2-2.
There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and Programmable Fun
without RAM/ROM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM, ROM and re
tions. The PFF block contains building blocks for logic, arithmetic and ROM functions. Both PFU and
are optimized for flexibility allowing complex designs to be implemented quickly and efficiently. Logic
arranged in a two-dimensional array. Only one type of block is used per row. The PFU blocks are used
side rows. The rest of the core consists of rows of PFF blocks interspersed with rows of PFU blocks
three rows of PFF blocks there is a row of PFU blocks.
Each PIC block encompasses two PIOs (PIO pairs) with their respective sysIO interfaces. PIO pairs on
right edges of the device can be configured as LVDS transmit/receive pairs. sysMEM EBRs are large de
memory blocks. They can be configured as RAM or ROM.
The PFU, PFF, PIC and EBR Blocks are arranged in a two-dimensional grid with rows and columns a
Figure 2-1. The blocks are connected with many vertical and horizontal routing channel resources. Th
route software tool automatically allocates these routing resources.
At the end of the rows containing the sysMEM Blocks are the sysCLOCK Phase Locked Loop (PLL) Bl
PLLs have multiply, divide and phase shifting capability; they are used to manage the phase relation
clocks. The LatticeECP/EC architecture provides up to four PLLs per device.
Every device in the family has a JTAG Port with internal Logic Analyzer (ispTRACY) capability. The sys
port which allows for serial or parallel device configuration. The LatticeECP/EC devices use 1.2V as the
age.
© 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/lega
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change
www.latticesemi.com
2-1
Arch
Lattice Semiconductor
Arc
LatticeECP/EC Family Da
Figure 2-1. Simplified Block Diagram, LatticeECP/EC Device (Top Level)
Programmable I/O Cell
(PIC) includes sysIO
Interface
sysMEM
Block RA
JTAG Po
sysCONFIG Programming
Port (includes dedicated
and dual use pins)
PFF (PFU
RAM)
sysCLOC
Programmable
Functional Unit (PFU)
Figure 2-2. Simplified Block Diagram, LatticeECP-DSP Device (Top Level)
Programmable I/O Cell
(PIC) includes sysIO
Interface
sysMEM
Block RA
JTAG Po
sysCONFIG Programming
Port (includes dedicated
and dual use pins)
PFF (Fas
without R
sysDSP Block
sysCLOC
Programmable
Functional Unit (PFU)
2-2
FPGA/CPLD
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