LH28F004SU-Z1
FEATURES
40-PIN TSOP
4M (512K × 8) Flash Memory
TOP VIEW
•
512K × 8 Word Configuration
•
5 V Write/Erase Operation (5 V V
PP
)
– No Requirement for DC/DC Converter
to Write/Erase
A
16
A
15
A
14
A
13
A
12
A
11
A
9
A
8
WE
RP
V
PP
RY/BY
A
18
A
7
A
6
A
5
A
4
A
3
A
2
A
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A
17
GND
NC
NC
A
10
DQ
7
DQ
6
DQ
5
DQ
4
V
CC
V
CC
NC
DQ
3
DQ
2
DQ
1
DQ
0
OE
GND
CE
A
0
•
•
•
•
100 ns Maximum Access Time
32 Independently Lockable Blocks (16K)
100,000 Erase Cycles per Block
Automated Byte Write/Block Erase
– Command User Interface
– Status Register
»
– RY
/BY
»
Status Output
– Erase Suspend for Read
– Two-Byte Write
– Full Chip Erase
•
System Performance Enhancement
•
Data Protection
– Hardware Erase/Write Lockout during
Power Transitions
– Software Erase/Write Lockout
•
Independently Lockable for Write/Erase
on Each Block (Lock Block and Protect
Set/Reset)
28F004SUT-Z1-1
Figure 1. TSOP Configuration
•
5 µA (Typ.) I
CC
in CMOS Standby
•
0.2 µA (Typ.) Deep Power-Down
•
State-of-the-Art 0.55 µm ETOX™ Flash
Technology
•
40-pin, 1.2 mm × 10 mm × 20 mm TSOP
(Type I) Package
1
LH28F004SU-Z1
4M (512K × 8) Flash Memory
DQ
0
- DQ
7
OUTPUT
BUFFER
INPUT
BUFFER
ID
REGISTER
DATA
QUEUE
REGISTER
I/O
LOGIC
OUTPUT
MULTIPLEXER
CSR
REGISTER
ESRs
CE
OE
CUI
WE
RP
DATA
COMPARATOR
A
0
- A
18
INPUT
BUFFER
Y-DECODER
Y GATING/SENSING
16KB BLOCK 30
16KB BLOCK 31
16KB BLOCK 0
16KB BLOCK 1
WSM
RY/BY
ADDRESS
QUEUE
LATCH
...
X-DECODER
...
ADDRESS
COUNTER
...
PROGRAM/
ERASE
VOLTAGE
SWITCH
V
PP
V
CC
GND
28F004SUT-Z1-2
Figure 2. LH28F004SU-Z1 Block Diagram
2
4M (512K × 8) Flash Memory
LH28F004SU-Z1
PIN DESCRIPTION
SYMBOL
TYPE
NAME AND FUNCTION
WORD-SELECT ADDRESSES:
Select a word within one 16K block. These
addresses are latched during Data Writes.
BLOCK-SELECT ADDRESSES:
Select 1 of 32 Erase blocks. These addresses are
latched during Data Writes, Erase and Lock-Block operations.
DATA INPUT/OUTPUT:
Inputs data and commands during CUI write cycles.
Outputs array, buffer, identifier or status data in the appropriate Read mode.
Floated when the chip is de-selected or the outputs are disabled.
CHIP ENABLE INPUT:
Activate the device’s control logic, input buffers, decoders
and sense amplifiers. CE
»
must be low to select the device.
RESET/POWER-DOWN:
RP
»
low places the device in a Deep Power-Down state. All
circuits that burn static power, even those circuits enabled in standby mode, are
turned off. When returning from Deep Power-Down, a recovery time of 550 ns is
required to allow these circuits to power-up. When RP
»
goes low, any current or
pending WSM operation(s) are terminated, and the device is reset. All Status
Registers return to ready (with all status flags cleared).
OUTPUT ENABLE:
Gates device data through the output buffers when low. The
outputs float to tri-state off when OE
»
is high.
WRITE ENABLE:
Controls access to the CUI, Data Queue Registers and Address
Queue Latches. WE is active low, and latches both address and data (command or
array) on its rising edge.
READY/BUSY:
Indicates status of the internal WSM. When low, it indicates that the
WSM is busy performing an operation. When the WSM is ready for new operation
or Erase is Suspended, or the device is in deep power-down mode RY
»
/BY
»
pin is
floated.
ERASE/WRITE POWER SUPPLY (5.0 V ±0.5 V):
For erasing memory array blocks
or writing words/bytes into the flash array.
DEVICE POWER SUPPLY (5.0 V ±0.5 V):
Do not leave any power pins floating.
GROUND FOR ALL INTERNAL CIRCUITRY:
Do not leave any ground pins floating.
NO CONNECT:
No internal connection to die, lead may be driven or left floating
A
0
- A
13
A
14
- A
18
INPUT
INPUT
DQ
0
- DQ
7
INPUT/OUTPUT
CE
»
INPUT
RP
»
INPUT
OE
»
INPUT
WE
INPUT
RY
»
/BY
»
OPEN DRAIN
OUTPUT
V
PP
V
CC
GND
NC
SUPPLY
SUPPLY
SUPPLY
3
LH28F004SU-Z1
4M (512K × 8) Flash Memory
INTRODUCTION
Sharp’s LH28F004SU-Z1 4M Flash Memory is a revo-
lutionary architecture which enables the design of truly
mobile, high performance, personal computing and com-
munication products. With innovative capabilities, 5 V
single voltage operation and very high read/write per-
formance, the LH28F004SU-Z1 is also the ideal choice
for designing embedded mass storage flash memory
systems.
The LH28F004SU-Z1 is a very high density, highest
performance non-volatile read/write solution for solid-
state storage applications. Its independently lockable
32 symmetrical blocked architecture (16K each)
extended cycling, low power operation, very fast write
and read performance and selective block locking pro-
vide a highly flexible memory component suitable for
high density memory cards, Resident Flash Arrays and
PCMCIA-ATA Flash Drives. The LH28F004SU-Z1’s
single power supply operation enables the design of
memory cards which can be read/written in 5.0 V sys-
tems. Its x8 architecture allows the optimization of
memory to processor interface. The flexible block lock-
ing option enables bundling of executable application
software in a Resident Flash Array or memory card.
Manufactured on Sharp’s 0.55 µm ETOX™ process
technology, the LH28F004SU-Z1 is the most cost-
effective, high-density 5.0 V flash memory.
A Commander User Interface (CUI) serves as the
system interface between the microprocessor or
microcontroller and the internal memory operation.
Internal Algorithm Automation allows Byte Writes and
Block Erase operations to be executed using a Two-
Write command sequence to the CUI in the same way
as the LH28F008SA 8M Flash Memory.
A Superset of commands have been added to the
basic LH28F008SA command-set to achieve higher
write performance and provide additional capabilities.
These new commands and features include:
• Software Locking of Memory Blocks
• Memory Protection Set/Reset Capability
• Two-Byte Successive Writes in 8-bit Systems
• Erase All Unlocked Blocks
Writing of memory data is performed typically within
13 µs. A Block Erase operation erases one of the 32
blocks in typically 0.6 seconds, independent of the other
blocks.
LH28F004SU-Z1 allows to erase all unlocked blocks.
It is desirable in case you have to implement Erase op-
eration maxmum 32 times.
LH28F004SU-Z1 enablesTwo-Byte serialWrite which
is operated by three times command input. This feature
can improve system write performance by up to typi-
cally 10 µs per byte.
All operations are started by a sequence of Write
commands to the device. Status Register (described in
detail later) and a RY
»
/BY
»
output pin provide informa-
tion on the progress of the requested operation.
Same as the LH28F008SA, LH28F004SU-Z1
requires an operation to complete before the next
operation can be requested, also it allows to suspend
block erase to read data from any other block, and al-
low to resume erase operation.
The LH28F004SU-Z1 provides user-selectable block
locking to protect code or data such as Device Drivers,
PCMCIA card information, ROM-Executable OS or
Application Code. Each block has an associated non-
volatile lock-bit which determines the lock status of the
block. In addition, the LH28F004SU-Z1 has a software
controlled master Write Protect circuit which prevents
any modifications to memory blocks whose lock-bits are
set.
Description
The LH28F004SU-Z1 is a high perfor mance
4M (4,194,304 bit) block erasable non-volatile random
access memor y organized as 512K × 8. The
LH28F004SU-Z1 includes thirty-two 16K (16,384)
blocks. A chip memory map is shown in Figure 3.
The implementation of a new architecture, with many
enhanced features, will improve the device operating
characteristics and results in greater product reliability
and ease of use.
Among the significant enhancements of the
LH28F004SU-Z1:
• 5 V Read, Write/Erase Operations (5 V V
CC
, V
PP
)
• Low Power Capability
• Improved Write Performance
• Dedicated Block Write/Erase Protection
• Command-Controlled Memory Protection
Set/Reset Capability
The LH28F004SU-Z1 will be available in a 40-pin,
1.2 mm thick × 10 mm × 20 mm TSOP (Type I) pack-
age. This form factor and pinout allow for very high board
layout densities.
4
4M (512K × 8) Flash Memory
LH28F004SU-Z1
When the device power-up or RP
»
turns High, Write
Protect Set/Confirm command must be written. Other-
wise, all lock bits in the device remain being locked,
can’t perform the Write to each block and single Block
Erase. Write Protect Set/Confirm command must be
written to reflect the actual lock status. However, when
the device power-on or RP
»
turns High, Erase All Un-
locked Blocks can be used. If used, Erase is performed
with reflecting actual lock status, and after that Write
and Block Erase can be used.
The LH28F004SU-Z1 contains Status Register to
accomplish various functions:
• A Compatible Status Register (CSR) which is
100% compatible with the LH28F008SA Flash
Memory’s Status Register. This register, when used
alone, provides a straightforward upgrade capabil-
ity to the LH28F004SU-Z1 from a LH28F008SA
based design.
The LH28F004SU-Z1 incorporates an open drain
RY
»
/BY
»
output pin. This feature allows the user to OR-
tie many RY
/BY
»
pins together in a multiple memory con-
»
figuration such as a Resident Flash Array.
The LH28F004SU-Z1 is specified for a maximum
access time of 100 ns (t
ACC
) at 5 V operation (4.5 to
5.5 V) over the commercial temperature range (0 to
+70°C).
The LH28F004SU-Z1 incorporates an Automatic
Power Saving (APS) feature which substantially reduces
the active current when the device is in static mode of
operation (addresses not switching).
In APS mode, the typical I
CC
current is 2 mA at 5.0 V.
A Deep Power-Down mode of operation is invoked
when the RP
»
(called PWD on the LH28F008SA) pin
transitions low. This mode brings the device power con-
sumption to less than 5 µA, and provides additional write
protection by acting as a device reset pin during power
transitions. A reset time of 550 ns is required from RP
»
switching high until outputs are again valid. In the Deep
Power-Down state, the WSM is reset (any current
operation will abort) and the CSR register is cleared.
A CMOS Standby mode of operation is enabled when
CE
»
transitions high and RP
»
stays high with all input
control pins at CMOS levels. In this mode, the device
draws an I
CC
standby current of 10 µA.
MEMORY MAP
7FFFFH
7C000H
7BFFFH
78000H
77FFFH
74000H
73FFFH
70000H
6FFFFH
6C000H
6BFFFH
68000H
67FFFH
64000H
63FFFH
60000H
5FFFFH
5C000H
5BFFFH
58000H
57FFFH
54000H
53FFFH
50000H
4FFFFH
4C000H
4BFFFH
48000H
47FFFH
44000H
43FFFH
40000H
3FFFFH
3C000H
3BFFFH
38000H
37FFFH
34000H
33FFFH
30000H
2FFFFH
2C000H
2BFFFH
28000H
27FFFH
24000H
23FFFH
20000H
1FFFFH
1C000H
1BFFFH
18000H
17FFFH
14000H
13FFFH
10000H
0FFFFH
0C000H
0BFFFH
08000H
07FFFH
04000H
03FFFH
00000H
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
28F004SUT-Z1-3
Figure 3. Memory Map
5
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