nonvolatile, read/write storage solution for a wide
range of applications. Their symmetrically-blocked
architecture, flexible voltage and enhanced cycling
capability provide for highly flexible component
suitable for resident flash arrays, SIMMs and memory
cards. Their enhanced suspend capabilities provide
for an ideal solution for code + data storage
applications. For secure code storage applications,
such as networking, where code is either directly
executed out of flash or downloaded to DRAM, the
LH28F008SC-V/SCH-V offer three levels of
protection : absolute protection with V
PP
at GND,
selective hardware block locking, or flexible software
block locking. These alternatives give designers
ultimate control of their code security needs.
8 M-bit (1 MB x 8) Smart 5
Flash Memories
• Enhanced automated suspend options
– Byte write suspend to read
– Block erase suspend to byte write
– Block erase suspend to read
• Enhanced data protection features
– Absolute protection with V
PP
= GND
– Flexible block locking
– Block erase/byte write lockout during power
transitions
• SRAM-compatible write interface
• High-density symmetrically-blocked architecture
– Sixteen 64 k-byte erasable blocks
• Enhanced cycling capability
– 100 000 block erase cycles
– 1.6 million block erase cycles/chip
• Low power management
– Deep power-down mode
– Automatic power saving mode decreases I
CC
in static mode
• Automated byte write and block erase
– Command user interface
– Status register
• ETOX
TM
∗
V nonvolatile flash technology
• Packages
– 40-pin TSOP Type I (TSOP040-P-1020)
Normal bend/Reverse bend
– 44-pin SOP (SOP044-P-0600)
– 48-ball CSP (FBGA048-P-0608)
∗
ETOX is a trademark of Intel Corporation.
FEATURES
• Smart 5 technology
– 5 V V
CC
– 5 V or 12 V V
PP
• High performance read access time
LH28F008SC-V85/SCH-V85
– 85 ns (5.0±0.25 V)/90 ns (5.0±0.5 V)
LH28F008SC-V12/SCH-V12
– 120 ns (5.0±0.5 V)
COMPARISON TABLE
VERSIONS
LH28F008SC-V
LH28F008SCH-V
OPERATING TEMPERATURE
0 to +70
˚
C
–25 to +85
˚
C
DC CHARACTERISTICS
V
CC
deep power-down current (MAX.)
10 µA
20 µA
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books,
etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
-1-
LH28F008SC-V/SCH-V
PIN CONNECTIONS
40-PIN TSOP (Type I)
A
19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
CE#
V
CC
V
PP
RP#
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
44-PIN SOP
NC
NC
WE#
OE#
RY/BY#
DQ
7
DQ
6
DQ
5
DQ
4
V
CC
GND
GND
DQ
3
DQ
2
DQ
1
DQ
0
A
0
A
1
A
2
A
3
V
PP
RP#
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
NC
NC
A
3
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
DQ
3
GND
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
TOP VIEW
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
(TSOP040-P-1020)
V
CC
CE#
A
12
A
13
A
14
A
15
A
16
A
17
A
18
A
19
NC
NC
NC
NC
WE#
OE#
RY/BY#
DQ
7
DQ
6
DQ
5
DQ
4
V
CC
NOTE :
Reverse bend available on request.
(SOP044-P-0600)
48-BALL CSP
1
A
B
C
D
E
F
A
5
A
6
A
4
A
3
A
1
A
2
2
A
8
A
9
A
7
A
0
DQ
1
DQ
0
3
A
11
RP#
A
10
DQ
2
GND
DQ
3
4
V
PP
NC
NC
NC
NC
GND
5
V
CC
NC
NC
NC
NC
V
CC
6
A
12
CE#
A
13
DQ
6
DQ
4
DQ
5
7
A
15
A
14
A
16
RY/BY#
8
A
18
A
17
A
19
NC
OE#
WE#
DQ
7
NC
(FBGA048-P-0608)
-2-
LH28F008SC-V/SCH-V
BLOCK DIAGRAM
DQ
0
-DQ
7
OUTPUT
BUFFER
INPUT
BUFFER
OUTPUT
MULTIPLEXER
IDENTIFIER
REGISTER
DATA
REGISTER
I/O
LOGIC
V
CC
CE#
STATUS
REGISTER
COMMAND
USER
INTERFACE
WE#
OE#
RP#
DATA
COMPARATOR
A
0
-A
19
INPUT
BUFFER
Y DECODER
Y GATING
WRITE
STATE
MACHINE
RY/BY#
PROGRAM/ERASE
VOLTAGE SWITCH
V
PP
ADDRESS
LATCH
X DECODER
16
64 k-BYTE
BLOCKS
V
CC
GND
ADDRESS
COUNTER
-3-
LH28F008SC-V/SCH-V
PIN DESCRIPTION
SYMBOL
A
0
-A
19
TYPE
INPUT
NAME AND FUNCTION
ADDRESS INPUTS :
Inputs for addresses during read and write operations. Addresses
are internally latched during a write cycle.
DATA INPUT/OUTPUTS :
Inputs data and commands during CUI write cycles; outputs
DQ
0
-DQ
7
INPUT/
OUTPUT
data during memory array, status register, and identifier code read cycles. Data pins
float to high-impedance when the chip is deselected or outputs are disabled. Data is
internally latched during a write cycle.
CHIP ENABLE :
Activates the device's control logic, input buffers, decoders, and sense
CE#
INPUT
amplifiers. CE#-high deselects the device and reduces power consumption to standby
levels.
RESET/DEEP POWER-DOWN :
Puts the device in deep power-down mode and resets
internal automation. RP#-high enables normal operation. When driven low, RP# inhibits
write operations which provide data protection during power transitions. Exit from deep
RP#
INPUT
power-down sets the device to read array mode. RP# at V
HH
enables setting of the
master lock-bit and enables configuration of block lock-bits when the master lock-bit is
set. RP# = V
HH
overrides block lock-bits thereby enabling block erase and byte write
operations to locked memory blocks. Block erase, byte write, or lock-bit configuration
with V
IH
≤
RP#
≤
V
HH
produce spurious results and should not be attempted.
OE#
WE#
INPUT
INPUT
OUTPUT ENABLE :
Gates the device's outputs during a read cycle.
WRITE ENABLE :
Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of the WE# pulse.
READY/BUSY :
Indicates the status of the internal WSM. When low, the WSM is
performing an internal operation (block erase, byte write, or lock-bit configuration).
RY/BY#
OUTPUT
RY/BY#-high indicates that the WSM is ready for new commands, block erase is
suspended, and byte write is inactive, byte write is suspended, or the device is in deep
power-down mode. RY/BY# is always active and does not float when the chip is
deselected or data outputs are disabled.
BLOCK ERASE, BYTE WRITE, LOCK-BIT CONFIGURATION POWER SUPPLY :
For
V
PP
SUPPLY
erasing array blocks, writing bytes, or configuring lock-bits. With V
PP
≤
V
PPLK
, memory
contents cannot be altered. Block erase, byte write, and lock-bit configuration with an
invalid V
PP
(see
Section 6.2.3 "DC CHARACTERISTICS")
produce spurious results
and should not be attempted.
DEVICE POWER SUPPLY :
Internal detection configures the device for 5 V operation.
V
CC
SUPPLY
Do not float any power pins. With V
CC
≤
V
LKO
, all write attempts to the flash memory
are inhibited. Device operations at invalid V
CC
voltage (see
Section 6.2.3 "DC
CHARACTERISTICS")
produce spurious results and should not be attempted.
GROUND :
Do not float any ground pins.
NO CONNECT :
Lead is not internal connected; recommend to be floated.
GND
NC
SUPPLY
-4-
LH28F008SC-V/SCH-V
1 INTRODUCTION
This datasheet contains LH28F008SC-V/SCH-V
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4, and 5 describe the
memory organization and functionality. Section 6
covers electrical specifications. LH28F008SC-V/
SCH-V flash memories documentation also
includes ordering information which is referenced in
Section 7.
erasable, lockable, and unlockable in-system. The
memory map is shown in
Fig.1.
Smart 5 technology provides a choice of V
CC
and
V
PP
combinations, as shown in
Table 1,
to meet
system performance and power expectations. V
PP
at 5 V eliminates the need for a separate 12 V
converter, while V
PP
= 12 V maximizes block erase
and byte write performance. In addition to flexible
erase and program voltages, the dedicated V
PP
pin
gives complete data protection when V
PP
≤
V
PPLK
.
Table 1 V
CC
and V
PP
Voltage Combinations
Offered by Smart 5 Technology
V
CC
VOLTAGE
V
PP
VOLTAGE
5 V, 12 V
5V
1.1
New Features
LH28F008SC-V/SCH-V Smart 5 flash memories
maintain
backwards-compatibility
with
the
LH28F008SA. Key enhancements over the
LH28F008SA include :
• Smart 5 Technology
• Enhanced Suspend Capabilities
• In-System Block Locking
Both devices share a compatible pinout, status
register, and software command set. These
similarities enable a clean upgrade from the
LH28F008SA to LH28F008SC-V/SCH-V. When
upgrading, it is important to note the following
differences :
• Because of new feature support, the two
devices have different device codes. This
allows for software optimization.
• V
PPLK
has been lowered from 6.5 V to 1.5 V to
support 5 V block erase, byte write, and lock-bit
configuration operations. Designs that switch
V
PP
off during read operations should make
sure that the V
PP
voltage transitions to GND.
• To take advantage of Smart 5 technology, allow
V
PP
connection to 5 V.
Internal V
CC
and V
PP
detection circuitry auto-
matically configures the device for optimized read
and write operations.
A Command User Interface (CUI) serves as the
interface between the system processor and
internal operation of the device. A valid command
sequence written to the CUI initiates device
automation. An internal Write State Machine (WSM)
automatically executes the algorithms and timings
necessary for block erase, byte write, and lock-bit
configuration operations.
A block erase operation erases one of the device’s
64 k-byte blocks typically within 1 second (5 V V
CC
,
12 V V
PP
) independent of other blocks. Each block
can be independently erased 100 000 times (1.6
million block erases per device). Block erase
suspend mode allows system software to suspend
block erase to read data from, or write data to any
other block.
Writing memory data is performed in byte
increments typically within 6 µs (5 V V
CC
, 12 V
V
PP
). Byte write suspend mode enables the system
1.2
Product Overview
The LH28F008SC-V/SCH-V are high-performance
8 M-bit Smart 5 flash memories organized as 1 M-
byte of 8 bits. The 1 M-byte of data is arranged in
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
