16M (1M × 16, 2M × 8) Flash Memory
LH28F016LL
PIN DESCRIPTION
SYMBOL
TYPE
NAME AND FUNCTION
BYTE-SELECT ADDRESS:
Selects between high and low byte when device is in x8
mode. This address is latched in x8 Data Writes. Not used in x16 mode (i.e., the A
0
input buffer is turned off when BYTE is high).
WORD-SELECT ADDRESSES:
Select a word within one 64K block. A
6
-
A
15
selects
1 of 1024 rows, and A
1
- A
5
selects 16 of 512 columns. These addresses are
latched during Data Writes.
BLOCK-SELECT ADDRESSES:
Select 1 of 32 Erase blocks. These addresses are
latched during Data Writes, Erase and Lock-Block operations.
LOW-BYTE DATA BUS:
Inputs data and commands during CUI write cycles.
Outputs array, buffer, identifier or status data in the appropriate Read mode. Floated
when the chip is de-selected or the outputs are disabled.
HIGH-BYTE DATA BUS
: Inputs data during x16 Data-Write operations. Outputs
array, buffer or identifier data in the appropriate Read mode; not used for Status
register reads. Floated when the chip is de-selected or the outputs are disabled.
CHIP ENABLE INPUTS
: Activate the device’s control logic, input buffers, decoders and
sense amplifiers. With either CE
»
0
or CE
»
1
high, the device is de-selected and power
consumption reduces to Standby levels upon completion of any current Data-Write or
Erase operations. Both CE
»
0
, CE
»
1
must be low to select the device. All timing
specifications are the same for both signals. Device Selection
occ
urs with the latter
falling edge of CE
»
0
or CE
»
1
. The first rising edge of CE
»
0
or CE
»
1
disables the device.
RESET/POWER-DOWN:
RP
»
low places the device in a Deep Power-Down state. All
circuits that burn static power, even those circuits enabled in standby mode, are turned
off. When returning from Deep Power-Down, a recovery time of 5 ns is required to
allow these circuits to power-up for Read mode, and another 395 ns is required to enter
Program or Erase mode. When RP
»
goes low, any current or pending WSM operation(s)
are terminated, and the device is reset. All Status registers return to ready (with all
status flags cleared).
OUTPUT ENABLE:
Gates device data through the output buffers when low. The
outputs float to tri-state off when OE
»
is high.
NOTE:
CE
»
X
overrides OE
»
, and OE
»
overrides WE.
WRITE ENABLE:
Controls access to the CUI, Page Buffers, Data Queue Registers
and Address Queue Latches. WE is active low, and latches both address and data
(command or array) on its rising edge.
READY/BUSY:
Indicates status of the internal WSM. When low, it indicates that the
WSM is busy performing an operation. RY
»
/BY
»
high indicates that the WSM is ready
for new operations (or WSM has completed all pending operations), or Erase is
Suspended, or the device is in deep power-down mode. This output is always active
(i.e., not floated to tri-state off when OE
»
or CE
»
0
, CE
»
1
are high), except if a RY
»
/BY
»
Pin Disable command is issued.
A
0
INPUT
A
1
- A
15
INPUT
A
16
- A
20
INPUT
DQ
0
- DQ
7
INPUT/OUTPUT
DQ
8
- DQ
15
INPUT/OUTPUT
CE
»
0
, CE
»
1
INPUT
RP
»
INPUT
OE
»
INPUT
WE
INPUT
RY
»
/BY
»
OPEN DRAIN
OUTPUT
3
LH28F016LL
16M (1M × 16, 2M × 8) Flash Memory
PIN DESCRIPTION (Continued)
SYMBOL
TYPE
NAME AND FUNCTION
WRITE PROTECT:
Erase blocks can be locked by writing a non-volatile lock-bit for
each block. When WP is low, those locked blocks as reflected by the Block-Lock Status
bits (BSR.6), are protected from inadvertent Data Writes or Erases. When WP is high,
all blocks can be Written or Erased regardless of the state of the lock-bits. The WP
input buffer is disabled when RP
»
transitions low (deep power-down mode).
BYTE ENABLE:
BYTE low places device in x8 mode. All data is then input or output
on DQ
0
- DQ
7
, and DQ
8
- DQ
15
float. Address A
0
selects between the high and low
byte. BYTE high places the device in x16 mode, and turns off the A
0
input buffer.
Address A
1
, then becomes the lowest order address.
INPUT FROM OUTSIDE INDUCTOR:
Input pin for outside inductor in DC/DC
converter circuit. Connect 1.8 (µH) inductor from V
CC
.
INPUT FROM OUTSIDE CAPACITOR:
Input pin for outside capacitor in DC/DC
converter circuit. Ground at 22000 (pF) capacitor.
DEVICE POWER SUPPLY 3.0 V (2.7 V to 3.6 V)
: Do not leave any power pins floating.
GROUND FOR ALL INTERNAL CIRCUITRY:
Do not leave any ground pins floating.
NO CONNECT:
No internal connection to die, lead may be driven or left floating.
GROUND
WP
INPUT
BYTE
INPUT
LX
LC
V
CC
GND
NC
V
SS
L
INPUT
INPUT
SUPPLY
SUPPLY
4
16M (1M × 16, 2M × 8) Flash Memory
LH28F016LL
INTRODUCTION
Sharp’s LH28F016LL 16M Flash Memory is a revo-
lutionary architecture which enables the design of truly
mobile, high performance, personal computing and com-
munication products. With innovative capabilities,
3 V single voltage operation and very high read/write
performance, the LH28F0166LL is also the ideal choice
for designing embedded mass storage flash memory
systems.
The LH28F016LL is very high density, highest per-
formance non-volatile read/write solution for solid-state
storage applications. Its symmetrically blocked archi-
tecture (100% compatible with the LH28F016SU 16M
Flash memory), extended cycling, minimum power
2.7 V operation, very fast write and read performance
and selective block locking provide a highly flexible
memory component suitable for battery operation por-
table equipment such as digital still camera, PDA, cel-
lular phone, and memory card. Its x8/x16 architecture
allows the optimization of memory to processor inter-
face. The flexible block locking option enables bundling
of executable of executable application software in a
Resident Flash Array or memory card. Manufactured
on Sharp’s 0.6 µm ETOX™ process technology, the
LH28F016LL is the most cost-effective, high-density
3 V single power operation flash memory.
Internal Algorithm Automation allows Byte/Word
Writes and Block Erase operations to be executed us-
ing a Two-Write command sequence to the CUI in the
same way as the LH28F008SA 8M Flash memory.
A Superset of commands have been added to the
basic LH28F008SA command-set to achieve higher
write performance and provide additional capabilities.
These new commands and features include:
•
•
•
•
•
•
Page Buffer Writes to Flash
Command Queuing Capability
Automatic Data Writes During Erase
Software Locking of Memory Blocks
Two-Byte Successive Writes in 8-bit Systems
Erase All Unlocked Blocks
Writing of memory data is performed in either byte or
word increments typically within 9 µs, a 15% improve-
ment over the LH28F008SA.
Each block can be written and erased a minimum of
100,000 cycles. Systems can achieve 1,000,000 Block
Erase Cycles by providing wear-leveling algorithms and
graceful block retirement. These techniques have
already been employed in many flash file systems and
Hard Disk Drive designs.
The LH28F016LL incorporates two Page Buffers of
256 Bytes (128 Words) each to allow page data writes.
This feature can improve a system write performance
by up to 4.8 times over previous flash memory devices.
All operations are started by a sequence of Write
commands to the device. Three Status Registers (de-
scribed in detail later) and a RY
»
/BY
»
output pin provide
information on the progress of the requested operation.
While the LH28F008SA requires an operation to com-
plete before the next operation can be requested, the
LH28F016LL allows queuing of the next operation while
the memory executes the current operation. This elimi-
nates system overhead when writing several bytes in a
row to the array or erasing several blocks at the same
time. The LH28F016LL can also perform write opera-
tions to one block of memory while performing erase of
another block.
The LH28F016LL provides user-selectable block
locking to protect code or data such as Device Drivers,
PCMCIA card information, ROM-Executable O/S or
Application Code. Each block has an associated non-
volatile lock-bit which determines the lock status of the
block. In addition, the LH28F016LL has a master Write
Protect pin (WP
»
) which prevents any modifications to
memory blocks whose lock-bits are set.
DESCRIPTION
The LH28F016LL is a high performance 16M
(16,777,216 bit) block erasable non-volatile random
access memory organized as either 1M × 16 or 2M x 8.
The LH28F016LL includes thirty-two 64K (65,536)
blocks or thirty-two 32-KW (32,768) blocks. A chip
memory map is shown in Figure 3.
The implementation of a new architecture, with many
enhanced features, will improve the device operating
characteristics and results in greater product reliability
and ease of use.
Among the significant enhancements of the
LH28F016LL:
•
•
•
•
3 V Write/Erase Operation (3 V V
PP
)
3 V Low Power Capability
Improved Write Performance
Dedicated Block Write/Erase Protection
The LH28F016LL will be available in a 56-pin,
1.2 mm thick × 14 mm × 20 mm TSOP (Type I) pack-
age. This form factor and pinout allow for very high board
layout densities.
A Command User Interface (CUI) serves as the sys-
tem interface between the microprocessor or
microcontroller and the internal memory operation.
5
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