LH5164AZ8
FEATURES
•
8,192
×
8 bit organization
•
Access time:
200 ns (V
CC
= 3.0 V MAX.)
•
Power consumption:
Operating:
60 mW (MAX.) @ 3 V
Standby (to 60°C):
3
µW
(MAX.) @ 3 V
Data hold
0.6
µA
(V
CC
= 3 V, T
A
= 60°C)
•
Operating voltage range:
3.0 V to 3.6 V
•
Wide operating temperature range:
-30 to 60°C
•
Fully-static operation
•
TTL compatible I/O
•
Three-state outputs
•
Package: 28-pin, 450-mil SOP
CMOS 64K (8K
×
8) Static RAM
DESCRIPTION
The LH5164AZ8 is a static RAM organized as
8,192
×
8 bits. It is fabricated using silicon-gate CMOS
process technology.
PIN CONNECTIONS
28-PIN SOP
NC
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
1
I/O
2
I/O
3
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
CE
2
A
8
A
9
A
11
OE
A
10
CE
1
I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
5164AZ8-1
TOP VIEW
Figure 1. Pin Connections for SOP Package
1
LH5164AZ8
CMOS 64K (8K
×
8) Static RAM
ROW ADDRESS
BUFFERS
ROW SELECT
A
9
24
A
8
25
A
12
2
A
7
3
A
6
4
A
5
5
A
4
6
A
3
7
MEMORY
ARRAY
(256 x 256)
28 V
CC
14 GND
I/O
1
11
I/O
2
12
I/O
3
13
I/O
4
15
I/O
5
16
I/O
6
17
I/O
7
18
I/O
8
19
INPUT
DATA
CONTROL
COLUMN I/O
CIRCUITS
COLUMN SELECT
COLUMN ADDRESS
BUFFERS
WE 27
OE 22
CE
2
26
CE
1
20
8
A
2
9
A
1
10
A
0
23
A
11
21
A
10
5164AZ8-2
Figure 2. LH5164AZ8 Block Diagram
PIN DESCRIPTION
SIGNAL
PIN NAME
SIGNAL
PIN NAME
A
0
- A
12
CE
1
- CE
2
WE
OE
Address inputs
Chip Enable input
Write Enable input
Output Enable input
I/O
1
- I/O
8
V
CC
GND
NC
Data inputs and outputs
Power supply
Ground
Non connection
2
CMOS 64K (8K
×
8) Static RAM
LH5164AZ8
TRUTH TABLE
CE
1
CE
2
WE
OE
MODE
I/O
1
- I/O
8
SUPPLY CURRENT
NOTE
H
X
L
L
L
NOTE:
1. X = H or L
X
L
H
H
H
X
X
L
H
H
X
X
X
L
H
Standby
Standby
Write
Read
Output deselect
High-Z
High-Z
D
IN
D
OUT
High-Z
Standby (I
SB
)
Standby (I
SB
)
Operating (I
CC
)
Operating (I
CC
)
Operating (I
CC
)
1
1
1
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNIT
NOTE
Supply voltage
Input voltage
Operating temperature
Storage temperature
V
CC
V
IN
Topr
Tstg
-0.3 to +7.0
-0.3 to V
CC
+ 0.3
-30 to +60
-65 to +150
V
V
°C
°C
1
1
NOTE:
1. The maximum applicable voltage on any pin with respect to GND.
RECOMMENDED OPERATING CONDITIONS (T
A
= -30 to +60°C)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Supply voltage
Input voltage
(V
CC
= 3.0 to 3.6 V)
V
CC
V
IH
V
IL
3.0
V
CC
- 0.5
-0.3
3.6
V
CC
+ 0.3
0.2
V
V
V
DC CHARACTERISTICS (T
A
= -30 to +60°C, V
CC
= 3.0 to 3.6 V)
ADD TABLE
NOTE:
1. CE
2
should be
≥
V
CC
- 0.2 V or
≤
0.2 V.
3
LH5164AZ8
CMOS 64K (8K
×
8) Static RAM
AC CHARACTERISTICS
(1) READ CYCLE (T
A
= -30 to +60°C, V
CC
= 3.0 to 3.6 V)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
Read cycle
Address access time
Chip enable
access time
(CE
1
)
(CE
2
)
t
RC
t
AA
t
ACE1
t
ACE2
t
OE
t
OH
(CE
1
)
(CE
2
)
(CE
1
)
(CE
2
)
t
LZ1
t
LZ2
t
OLZ
t
HZ1
t
HZ2
t
OHZ
200
200
200
200
150
10
20
20
10
0
0
0
60
60
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Output enable access time
Output hold time
Chip enable to
output in Low-Z
Output enable to output in Low-Z
Chip enable to
output in High-Z
Output disable to output in High-Z
(2) WRITE CYCLE (T
A
= -30 to +60°C, V
CC
= 3.0 to 3.6 V)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
Write cycle time
Chip enable to end of write
Address valid to end of write
Address setup time
Write pulse width
Write recovery time
Data valid to end of write
Data hold time
Output active from end of write
WE to output in High-Z
OE to output in High-Z
t
WC
t
CW
t
AW
t
AS
t
WP
t
WR
t
DW
t
DH
t
OW
t
WZ
t
OHZ
200
180
180
0
150
0
100
0
20
0
0
60
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AC TEST CONDITIONS
PARAMETER
MODE
Input voltage amplitude
Input rise/fall time
Timing reference level
Output load conditions
0 to V
CC
10 ns
1.5 V
No load
CAPACITANCE (T
A
= 25°C, f = 1 MHz)
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Input capacitance
Input/output capacitance
C
IN
C
I/O
V
IN
= 0 V
V
I/O
= 0 V
7
10
pF
pF
NOTE:
This parameter is sampled and not production tested.
4
CMOS 64K (8K
×
8) Static RAM
LH5164AZ8
DATA RETENTION CHARACTERISTICS (T
A
= -30 to +60°C)
PARAMETER
SYMBOL
CONDITIONS
MIN.
MAX.
UNIT
NOTE
Data retention supply voltage
Data retention supply current
Chip disable to data retention
Recovery time
V
CCDR
I
CCDR
t
CDR
t
R
CE
2
≤
0.2 V or
CE
1
≥
V
CCDR
– 0.2 V
V
CCDR
= 3.0 V,
CE
2
≤
0.2 V or
CE
1
≥
V
CCDR
– 0.2 V
T
A
= 25°C
T
A
= 60°C
2.0
5.5
0.2
0.6
V
µA
ns
ns
1
1
0
t
RC
2
NOTES:
1. CE
2
should be
≥
V
CCDR
- 0.2 V or
≤
0.2 V.
2. t
RC
= Read cycle time
t
RC
ADDRESS
t
AA
t
ACE1
CE
1
t
LZ1
t
ACE2
t
HZ1
CE
2
t
LZ2
t
OE
t
OLZ
t
HZ2
OE
t
OHZ
t
OH
D
OUT
NOTE:
WE is "HIGH" level during the read cycle.
DATA VALID
5164AZ8-3
Figure 3. Read Cycle
5
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