LH5116S
FEATURES
•
2,048
×
8 bit organization
•
Access time: 1000 ns (MAX.)
•
Low-power consumption:
Operating: 33 mW (MAX.)
Standby: 3.3
µW
(MAX.)
•
Fully-static operation
•
Three-state outputs
•
Single +3 V power supply
•
Package: 24-pin, 450-mil SOP
DESCRIPTION
The LH5116S is a static RAM organized as 2,048
×
8
bits. It is fabricated using silicon-gate CMOS process
technology. It operates at a low supply voltage of
3 V
±10%.
CMOS 16K (2K
×
8) Static RAM
PIN CONNECTIONS
24-PIN SOP
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
1
I/O
2
I/O
3
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
A
8
A
9
WE
OE
A
10
CE
I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
5116S-1
TOP VIEW
Figure 1. Pin Connections for SOP Package
1
LH5116S
CMOS 16K (2K
×
8) Static RAM
ROW DECODERS
ROW ADDRESS
BUFFERS
A
0
8
A
5
3
A
6
2
A
7
1
A
8
23
A
9
22
A
10
19
MEMORY CELL
ARRAY
(128 x128)
24 V
CC
12 GND
CE
DATA CONTROL
I/O
1
I/O
2
I/O
3
I/O
4
9
10
11
13
COLUMN
I/O CIRCUITS
I/O
5
14
I/O
6
15
I/O
7
16
I/O
8
17
COLUMN DECODERS
COLUMN ADDRESS
BUFFERS
CE
CE 18
WE 21
OE 20
4
A
4
5
A
3
6
A
2
7
A
1
5116S-2
Figure 2. LH5116S Block Diagram
PIN DESCRIPTION
SIGNAL
PIN NAME
SIGNAL
PIN NAME
A
0
- A
10
CE
OE
WE
Address input
Chip Enable input
Output Enable input
Write Enable input
I/O
1
- I/O
8
V
CC
GND
Data input/output
Power supply
Ground
TRUTH TABLE
CE
OE
WE
MODE
I/O
1
- I/O
8
SUPPLY CURRENT
NOTE
L
L
H
L
NOTE:
1. X = H or L
X
L
X
H
L
H
X
X
Write
Read
Deselect
Output disable
D
IN
D
OUT
High-Z
High-Z
Operating (I
CC
)
Operating (I
CC
)
Standby (I
SB
)
Operating (I
CC
)
1
1
1
2
CMOS 16K (2K
×
8) Static RAM
LH5116S
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNIT
NOTE
Supply voltage
Input voltage
Operating temperature
Storage temperature
V
CC
V
IN
Topr
Tstg
-0.3 to +7.0
-0.3 to V
CC
+0.3
0 to +50
-55 to +150
V
V
°C
°C
1
1
NOTE:
1. The maximum applicable voltage on any pin with respect to GND.
RECOMMENDED OPERATING CONDITIONS (T
A
= 0 to +50°C)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Supply voltage
Input voltage
V
CC
V
IH
V
IL
2.7
2.2
-0.3
3.0
3.3
V
CC
+ 0.3
0.8
V
V
V
DC CHARACTERISTICS (V
CC
= 3 V
±10%,
T
A
= 0 to +50°C)
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
NOTE
Output ‘LOW’ voltage
Output ‘HIGH’ voltage
Input leakage current
Output leakage current
Operating current
Standby current
V
OL
V
OH
I
LI
I
LO
I
CC1
I
CC2
I
CCL
I
OL
= 2.1 mA
I
OH
= -1.0 mA
V
IN
= 0 V to V
CC
CE = V
IH
, V
I/O
= 0 V to V
CC
Outputs open (OE = V
CC
)
Outputs open (OE = V
IH
)
CE
≥
V
CC
- 0.2 V
All other input pins = 0 V to V
CC
V
CC
- 0.5
-1.0
-1.0
8
8
0.5
1.0
1.0
10
10
1.0
V
V
µA
µA
mA
mA
µA
1
2
NOTES:
1. CE = 0 V; all other input pins = 0 V to V
CC
2. CE = V
IL
; all other input pins = V
IL
to V
IH
AC CHARACTERISTICS (V
CC
= 3 V
±10%,
T
A
= 0 to +50°C)
(1) READ CYCLE
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTE
Read cycle time
Address access time
Chip enable access time
Chip enable Low to output in Low-Z
Output enable access time
Output enable Low to output in Low-Z
Chip disable to output in High-Z
Output enable to output in High-Z
Output hold time
t
RC
t
AA
t
ACE
t
CLZ
t
OE
t
OLZ
t
CHZ
t
OHZ
t
OH
1000
1000
1000
10
100
10
0
0
10
40
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
1
1
NOTE:
1. Active output to high-impedance and high-impedance to output
active tests specified for a
±200
mV transition
from steady state levels into the test load.
3
LH5116S
CMOS 16K (2K
×
8) Static RAM
(2) WRITE CYCLE (V
CC
= 3 V
±10%,
T
A
= 0 to +50°C)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTE
Write cycle time
Chip enable to end of write
Address valid time
Address setup time
Write pulse width
Write recovery time
WE Low to output in High-Z
Data valid to end of write
Data hold time
Output active from end of write
Output enable to output in High-Z
t
WC
t
CW
t
AW
t
AS
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
t
OHZ
1000
100
100
0
100
20
30
50
20
10
0
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
1
NOTE:
1. Active output to high-impedance and high-impedance to output
active tests specified for a
±200
mV transition
from steady state levels into the test load.
AC TEST CONDITIONS
PARAMETER
MODE
NOTE
Input voltage amplitude
Input rise/fall time
Timing reference level
Output load conditions
0 to V
CC
10 ns
1.5 V
C
L
(100 pF)
1
NOTE:
1. Includes scope and jig capacitance.
DATA RETENTION CHARACTERISTICS (T
A
= 0 to +50°C)
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
NOTE
Data retention voltage
Data retention current
Chip disable to data retention
Recovery time
NOTES:
1. T
A
= 25°C
2. t
RC
= Read cycle time
V
CCDR
I
CCDR
t
CDR
t
R
CE
≥
V
CCDR
- 0.2 V
CE
≥
V
CCDR
- 0.2 V,
V
CCDR
= 2.0 V
2.0
1.0
0.2
0
t
RC
V
µA
ns
ns
2
1
CAPACITANCE
1
(T
A
= 25°C, f = 1MHz)
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Input capacitance
Input/output capacitance
C
IN
C
I/O
V
IN
= 0 V
VI/O = 0 V
7
10
pF
pF
NOTE:
1. This parameter is sampled and not production tested.
4
CMOS 16K (2K
×
8) Static RAM
LH5116S
t
CDR
V
CC
2.5 V
2.2 V
V
CCDR
CE
0V
DATA RETENTION MODE
t
R
CE
≥
V
CCDR
-0.2 V
5116S-6
Figure 3. Low Voltage Data Retention
t
RC
A
0
- A
10
t
AA
t
ACE
CE
t
OE
OE
t
OLZ
t
CLZ
D
OUT
NOTE:
WE = "HIGH"
DATA VALID
t
OH
t
CHZ
t
OHZ
5116S-3
Figure 4. Read Cycle
5
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