LH5164ASH
FEATURES
•
8,192
×
8 bit organization
•
Access time: 500 ns (MAX.)
•
Power consumption:
Operating:
60 mW (MAX.) @ 3 V
Standby:
3
µW
(MAX.) @ 70°C @ 3 V
9
µW
(MAX.) @ 85°C @ 3 V
•
Fully-static operation
•
Three-state outputs
•
Wide operating voltage range:
2.5 V to 5.5 V
•
TTL compatible I/O
•
Wide temp. range
t
OPR
: -40 to +85°C
•
Packages:
28-pin, 450-mil SOP
28-pin, 8
×
13 mm
2
TSOP (Type I)
DESCRIPTION
The LH5164ASH is a static RAM organized as
8,192
×
8 bits. It is fabricated using silicon-gate CMOS
process technology.
It is designed for 2.5 to 5.5 V low voltage operation
and wide temperature range from -40 to +85°C.
CMOS 64K (8K
×
8) Static RAM
PIN CONNECTIONS
28-PIN SOP
TOP VIEW
NC
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
1
I/O
2
I/O
3
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
CE
2
A
8
A
9
A
11
OE
A
10
CE
1
I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
5164ASH-1
Figure 1. Pin Connections for SOP Package
28-PIN TSOP (Type I)
TOP VIEW
OE
A
11
A
9
A
8
CE
2
WE
V
CC
NC
A
12
A
7
A
6
A
5
A
4
A
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
10
CE
1
I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
GND
I/O
3
I/O
2
I/O
1
A
0
A
1
A
2
5164ASH-8
Figure 2. Pin Connections for TSOP Package
1
LH5164ASH
CMOS 64K (8K
×
8) Static RAM
A
3
7
ROW ADDRESS
BUFFERS
A
4
6
A
5
5
A
6
4
A
7
3
A
8
25
A
9
24
A
12
2
ROW DECODERS
MEMORY
ARRAY
(256 x 256)
28 V
CC
14 GND
I/O
1
11
I/O
2
12
I/O
3
13
I/O
4
15
I/O
5
16
I/O
6
17
I/O
7
18
I/O
8
19
I/O
CIRCUITS
DATA CONTROL
COLUMN DECODERS
COLUMN ADDRESS
BUFFERS
WE 27
OE 22
CE
2
26
CE
1
20
10
A
0
9
A
1
8
A
2
21
A
10
23
A
11
5164ASH-2
Figure 3. LH5164ASH Block Diagram
PIN DESCRIPTION
SIGNAL
PIN NAME
SIGNAL
PIN NAME
A
0
- A
12
CE
1
- CE
2
WE
OE
Address inputs
Chip Enable input
Write Enable input
Output Enable input
I/O
1
- I/O
8
V
CC
GND
NC
Data inputs and outputs
Power supply
Ground
No connection
2
CMOS 64K (8K
×
8) Static RAM
LH5164ASH
TRUTH TABLE
CE
1
CE
2
WE
OE
MODE
I/O
1
- I/O
8
SUPPLY CURRENT
NOTE
H
X
L
L
L
NOTE:
1. X = H or L
X
L
H
H
H
X
X
L
H
H
X
X
X
L
H
Deselect
Deselect
Write
Read
Output disable
High-Z
High-Z
D
IN
D
OUT
High-Z
Standby (I
SB
)
Standby (I
SB
)
Operating (I
CC
)
Operating (I
CC
)
Operating (I
CC
)
1
1
1
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNIT
NOTE
Supply voltage
Input voltage
Operating temperature
Storage temperature
V
CC
V
IN
Topr
Tstg
-0.3 to +7.0
-0.3 to V
CC
+0.3
-40 to +85
-65 to +150
V
V
°C
°C
1
1, 2
NOTES:
1. The maximum applicable voltage on any pin with respect to GND.
2. V
IN
(MIN.) = -3.0 V for pulse width
≤50
ns.
RECOMMENDED OPERATING CONDITIONS (T
A
= -40 to +85°C)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTE
Supply voltage
Input voltage
(V
CC
= 2.5 to 4.5 V)
Input voltage
(V
CC
= 4.5 to 5.5 V)
V
CC
V
IH
V
IL
V
IH
V
IL
2.5
V
CC
- 0.5
-0.3
2.2
-0.3
3.0
5.5
V
CC
+ 0.3
0.2
V
CC
+ 0.3
0.8
V
V
V
V
V
1
NOTE:
1. V
IN
(MIN.) = -3.0 V for pulse width
≤50
ns.
DC CHARACTERISTICS (T
A
= -40 to +85°C, V
CC
= 2.5 to 5.5 V)
PARAMETER
SYMBOL
CONDITIONS
MIN.
MAX.
UNIT
NOTE
Input leakage current
Output leakage
current
I
LI
I
LO
Operating supply
current
I
CC
Standby current
Output Low voltage
Output High voltage
I
SB
I
SB1
V
OL
V
OH
V
IN
= 0 to V
CC
CE
1
= V
IH
or CE
2
= V
IL
or OE = V
IH
or WE = V
IL
V
I/O
= 0 to V
CC
CE
1
= 0.2 V, V
IN
= 0.2 V or
V
CC
- 0.2 V
t
CYCLE
=
CE
2
= V
CC
- 0.2 V,
500 ns
Output open
CE
1
= 0.2 V, V
IN
= 0.2 V or
t
CYCLE
=
V
CC
- 0.2 V
CE
2
= V
CC
- 0.2 V,
1.0
µs
Output open
CE
1
= 0.2 V, V
IN
= 0.2 V or
t
CYCLE
=
V
CC
- 0.2 V
CE
2
= V
CC
- 0.2 V,
1.0
µs
Output open, V
CC
= 3.3 V
T
A
≤
+70°C
CE
2
≤
0.2 V or
CE
1
≥
V
CC
- 0.2 V
T
A
≤
+85°C
CE
1
= V
IH
or CE
2
= V
IL
I
OL
= 500
µA
I
OH
= -500
µA
-1.0
-1.0
1.0
1.0
µA
µA
20
10
mA
8
1.0
3.0
5
0.5
V
CC
- 0.5
µA
mA
V
V
1
2
NOTES:
1. CE
2
should be
≥
V
CC
- 0.2 V or
≤
0.2 V when CE
1
≥
V
CC
- 0.2
V.
2. V
OH
is 4.5 V (Min.) at V
CC
> 5 V.
3
LH5164ASH
CMOS 64K (8K
×
8) Static RAM
AC CHARACTERISTICS
(1) READ CYCLE (T
A
= -40 to +85°C, V
CC
= 2.5 to 5.5 V)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
Read cycle time
Address access time
Chip enable
access time
(CE
1
)
(CE
2
)
t
RC
t
AA
t
ACE1
t
ACE2
t
OE
t
OH
(CE
1
)
(CE
2
)
(CE
1
)
(CE
2
)
t
LZ1
t
LZ2
t
OLZ
t
HZ1
t
HZ2
t
OHZ
500
500
500
500
200
10
20
20
10
0
0
0
60
60
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Output enable access time
Output hold time
Chip enable to
output in Low-Z
Output enable to output in Low-Z
Chip enable to
output in High-Z
Output disable to output in High-Z
(2) WRITE CYCLE (T
A
= -40 to +85°C, V
CC
= 2.5 to 5.5 V)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
Write cycle time
Chip enable to end of write
Address valid to end of write
Address setup time
Write pulse width
Write recovery time
Data valid to end of write
Data hold time
Output active from end of write
WE to output in High-Z
OE to output in High-Z
t
WC
t
CW
t
AW
t
AS
t
WP
t
WR
t
DW
t
DH
t
OW
t
WZ
t
OHZ
500
250
250
100
150
50
100
0
20
0
0
60
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE:
1. Active output to high-impedance and high-impedance to output
active tests specified for a
±200
mV transition
from steady state levels into the test load.
AC TEST CONDITIONS
PARAMETER
MODE
NOTE
Input voltage amplitude
Input rise/fall time
Timing reference level
Output load conditions
NOTE:
1. Includes scope and jig capacitance.
0 to V
CC
10 ns
1.5 V
C
L
(100 pF)
1
CAPACITANCE (T
A
= 25°C, f = 1MHz)
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Input capacitance
Input/output capacitance
C
IN
C
I/O
V
IN
= 0 V
V
I/O
= 0 V
7
10
pF
pF
NOTE:
This parameter is sampled and not production tested.
4
CMOS 64K (8K
×
8) Static RAM
LH5164ASH
DATA RETENTION CHARACTERISTICS (T
A
= -40 to +85°C)
PARAMETER
SYMBOL
CONDITIONS
MIN.
MAX.
UNIT
NOTE
Data retention supply voltage
V
CCDR
CE
2
≤
0.2 V or
CE
1
≥
V
CCDR
– 0.2 V
V
CCDR
= 3 V,
CE
2
≤
0.2 V or
CE
1
≥
V
CCDR
– 0.2 V
T
A
= 25°C
T
A
= 40°C
2.0
5.5
0.2
0.4
0.6
V
µA
µA
µA
ns
ns
1
Data retention supply current
I
CCDR
t
CDR
t
R
1
Chip disable to data retention
Recovery time
0
t
RC
2
NOTES:
1. CE
2
should be
≥
V
CCDR
- 0.2 V or
≤
0.2 V when CE
1
≥
V
CCDR
- 0.2 V.
2. t
RC
= Read cycle time
CE
1
CONTROL
(NOTE)
V
CC
2.5 V
t
CDR
DATA RETENTION MODE
t
R
V
CC
- 0.5 V
V
CCDR
CE
1
0V
CE
1
≥
V
CCDR
- 0.2 V
CE
2
CONTROL
DATA RETENTION MODE
V
CC
2.5 V
CE
2
t
CDR
t
R
V
CCDR
0.2 V
0V
CE
2
≥
0.2 V
NOTE:
To control data hold at CE
1
, fix the input level of CE
2
between V
CCDR
to V
CCDR
- 0.2 V or 0 V to 0.2 V
during the data retention.
5164ASH-6
Figure 4. Low Voltage Data Retention
5
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