LH521028
FEATURES
•
Fast Access Times: 17/20/25/35 ns
•
Wide Word (18-Bits) for:
– Improved Performance
– Reduced Component Count
– Nine-bit Byte for Parity
•
Transparent Address Latch
•
Reduced Loading on Address Bus
•
Low-Power Stand-by Mode when
Deselected
•
TTL Compatible I/O
•
5 V
±
10% Supply
•
2 V Data Retention
•
JEDEC Standard Pinout
•
Package: 52-Pin PLCC
52-PIN PLCC
CMOS 64K
×
18 Static RAM
operations on the high and the low bytes. The Address
Latches are transparent when ALE is HIGH (for applica-
tions not requiring a latch), and are latched when ALE is
LOW. The Address Latches and the wide word help to
eliminate the need for external Address busbuffers and/or
latches.
Write cycles occur when Chip Enable (E), S
H
and/or
S
L
, and Write Enable (W) are LOW. The Byte-select
signals can be used for Byte-write operations by disabling
the other byte during the Write operation. Data is trans-
ferred from the DQ pins to the memory location specified
by the 16 address lines. The proper use of the Output
Enable control (G) can prevent bus contention.
When E and either S
H
or S
L
are LOW and W is HIGH,
a static Read will occur at the memory location specified
by the address lines. G must be brought LOW to enable
the outputs. Since the device is fully static in operation,
new Read cycles can be performed by simply changing
the address with ALE HIGH.
PIN CONNECTIONS
TOP VIEW
ALE
V
CC
V
SS
A
15
A
14
A
0
S
L
A
13
46
45
44
43
42
41
40
39
38
37
36
35
34
DQ
8
DQ
7
DQ
6
V
CC
V
SS
DQ
5
DQ
4
DQ
3
DQ
2
V
SS
V
CC
DQ
1
DQ
0
S
H
A
1
W
The LH521028 is a high-speed 1,179,648-bit CMOS
SRAM organized as 64K
×
18. A fast, efficient design is
obtained with a CMOS periphery and a matrix con-
structed with polysilicon load memory cells. The
LH521028 is available in a compact 52-Pin PLCC, which
along with the six pairs of supply terminals, provide for
reliable operation.
The control signals include Write Enable (W), Chip
Enable (E), High and Low Byte Select (S
L
and S
H
), Output
Enable (G) and Address Latch Enable (ALE). The wide
word provides for reduced component count, improved
density, reduced Address bus loading and improved per-
formance. The wide word also allows for byte-parity with
no additional RAM required.
This RAM is fully static in operation. The Chip Enable
(E) control permits Read and Write operations when
active (LOW) or places the RAM in a low-power standby
mode when inactive (HIGH).The Byte-select controls, S
H
and S
L
, are also used to enable or disable Read and Write
DQ
9
DQ
10
V
CC
V
SS
DQ
11
DQ
12
DQ
13
DQ
14
V
SS
V
CC
DQ
15
DQ
16
DQ
17
7
8
9
10
11
12
13
14
15
16
17
18
19
6 5
E
4 3 2 1 52 51 50 49 48 47
20
21 22 23 24 25 26 27 28 29 30 31 32 33
G
FUNCTIONAL DESCRIPTION
A
11
V
SS
V
CC
A
10
A
12
521028-1D
A
4
A
2
A
3
A
5
A
6
A
8
Figure 1. Pin Connections for PLCC Package
A
7
A
9
4-211
LH521028
CMOS 64K
×
18 Static RAM
ALE
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
...
DQ
0
TRANSPARENT LATCH
DQ
8
...
I/O
CIRCUIT
S
L
E
W
S
H
TRANSPARENT LATCH
A
15
A
14
A
13
A
12
...
ROW DECODE
BLOCK
DECODE
A
11
A
10
A
9
COLUMN
DECODE
MEMORY ARRAY
(65,536 x 18)
G
DQ
9
...
DQ
17
...
I/O
CIRCUIT
...
521028-12
Figure 2. LH521028 Block Diagram
4-212
CMOS 64K
×
18 Static RAM
LH521028
TRUTH TABLE
ADDRESS
E
S
H
S
L
ALE
G
W
DQ
0
-DQ
8
DQ
9
-DQ
17
MODE
I
CC
Don’t Care
Valid
Valid
Valid
Valid
Don’t Care
Valid
Valid
Valid
Valid
Don’t Care
H
L
L
L
L
L
L
L
L
L
L
X
L
H
L
L
L
L
H
L
H
L
X
H
L
L
L
L
H
L
L
H
L
H
H
H
H
H
L
H
H
H
H
L
X
L
L
L
H
L
X
X
X
X
X
X
H
H
H
H
H
L
L
L
L
L
High-Z
Active
High-Z
Active
High-Z
Data Out
Data In
Don’t Care
Data In
Don’t Care
Data In
High-Z
High-Z
Active
Active
High-Z
Data Out
Don’t Care
Data In
Data In
Don’t Care
Data In
Standby
Read
Read
Read
Read
Read
Write, low byte
Write, high byte
Write, both bytes
Write, inhibited
Write, both bytes
I
SB
I
CC1
I
CC1
I
CC1
I
CC1
I
CC1
I
CC1
I
CC1
I
CC1
I
CC1
I
CC1
NOTE:
X = Don’t Care, L = LOW, H = HIGH
PIN DESCRIPTIONS
PIN
SIGNAL
PIN
SIGNAL
PIN
SIGNAL
PIN
SIGNAL
1
2
3
4
5
6
7
8
9
10
11
12
13
V
SS
V
CC
S
L
S
H
E
A
0
A
1
DQ
9
DQ
10
V
CC
V
SS
DQ
11
DQ
12
14
15
16
17
18
19
20
21
22
23
24
25
26
DQ
13
DQ
14
V
SS
V
CC
DQ
15
DQ
16
DQ
17
A
2
A
3
A
4
A
5
A
6
A
7
27
28
29
30
31
32
33
34
35
36
37
38
39
V
SS
V
CC
A
8
A
9
A
10
A
11
A
12
DQ
0
DQ
1
V
CC
V
SS
DQ
2
DQ
3
40
41
42
43
44
45
46
47
48
49
50
51
52
DQ
4
DQ
5
V
SS
V
CC
DQ
6
DQ
7
DQ
8
A
13
A
14
A
15
G
ALE
W
4-213
LH521028
CMOS 64K
×
18 Static RAM
byte and prevent Read or Write operations. When the
Select signal is LOW and Chip Enable is LOW, a Read or
Write operation is performed at the location determined
by the contents of the Address bus. When Chip Enable is
HIGH, the Select signals are Don’t Care. Select Low (S
L
)
is assigned to DQ
0
– DQ
8
and Select High (S
H
) is
assigned to DQ
9
– DQ
17
.
ALE
Address Latch
Enable
Active High Input
PIN DEFINITIONS
V
CC
V
SS
Positive Supply Voltage Terminals
Reference Terminals
Input
A
0
– A
15
Address Bus
The Address bus is decoded to select one 18-bit word
out of the total 64K words for Read and Write operations.
E
Chip Enable
Active LOW Input
Chip Enable is used to enable the device for Read and
Write operations. When HIGH, both Read and Write
operations are disabled and the device is in a reduced
power state. When LOW, a Read or Write operation is
enabled.
W
Write Enable
Active LOW Input
The Address Latch Enable signal is used to control the
Transparent latches on the Address bus. The Latches are
transparent when HIGH and are latched when LOW. If
not required, Address Latch Enable may be tied HIGH,
leaving the Address bus in a transparent condition.
DQ
0
– DQ
17
Data Bus
Input/Output
Write Enable is used to select either Read or Write
operations when the device is enabled. When Write
Enable is HIGH and the device is Enabled, a Read
operation is selected. When Write Enable is LOW and the
device is enabled, a Write operation is selected. A Byte-
write operation is available by using the Byte-select con-
trols.
S
H
, S
L
Select High
Select Low
Active LOW Inputs
DQ
0
– DQ
8
comprise the Low byte, selected by S
L
,
and DQ
9
– DQ
17
comprise the High Data byte, selected
by S
H
. The Data Bus is in a high impedance input mode
during Write operations and standby. The Data bus is in
a low-impedance output mode during Read operations.
G
Output Enable
Active LOW Input
The Select High and Select Low signals, in conjunction
with the Chip Enable and Write Enable signals, allow the
selection of the individual bytes for Read and Write op-
erations. When High, the Select signal will deselect its
The Output Enable signal is used to control the output
buffers on the Data Input/Output bus. When G is HIGH,
all output buffers are forced to a high impedance condi-
tion. When G is LOW, the output buffers will become
active only during a Read operation (E and S
H
/ S
L
are
LOW, W is HIGH).
4-214
CMOS 64K
×
18 Static RAM
LH521028
ABSOLUTE MAXIMUM RATINGS
1
PARAMETER
RATING
V
CC
to V
SS
Potential
Input Voltage Range
DC Output Current
2
Storage Temperature Range
Power Dissipation (Package Limit)
–0.5 V to 7 V
–0.5 V to V
CC
+ 0.5 V
±
40 mA
–65
o
C to 150
o
C
2W
NOTES:
1. Stresses greater than those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the device. This is a stress rating for
transient conditions only. Functional operation of the device at these or any other conditions above those indicated in the ‘Operating Range’
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Outputs should not be shorted for more than 30 seconds. No more than one output should be shorted at any time.
OPERATING RANGES
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
o
C
T
A
V
CC
V
SS
V
IL
V
IH
Temperature, Ambient
Supply Voltage
Supply Voltage
Logic ‘0’ Input Voltage
1
Logic ‘1’ Input Voltage
0
4.5
0
–0.5
2.2
5.0
0
70
5.5
0
0.8
V
CC
+ 0.5
V
V
V
V
NOTE:
1. Negative undershoot of up to 3.0 V is permitted once per cycle.
DC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I
CC1
I
SB1
Operating Current
1
Standby Current
t
CYCLE
= minimum
E
≥
V
CC
– 0.2 V
V
IN
≥
V
CC
– 0.2 V or V
IN
≤
0.2 V
f=0
E
≥
V
IH
V
IN
= V
IH
or V
IL
V
IN
= 0 V to V
CC
V
IN
= 0 V to V
CC
I
OH
= –4.0 mA
I
OL
= 8.0 mA
–2
–2
2.4
300
4
mA
mA
I
SB2
I
LI
I
LO
V
OH
V
OL
Standby Current
Input Leakage Current
I/O Leakage Current
Output High Voltage
Output Low Voltage
50
2
2
mA
µA
µA
V
0.4
V
NOTE:
1. I
CC
is dependent upon output loading and cycle rates. Specified values are with outputs open.
4-215
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