LH531024
FEATURES
•
65,536 words
×
16 bit organization
•
Access time: 100 ns (MAX.)
•
Power consumption:
Operating: 412.5 mW (MAX.)
Standby: 550
µW
(MAX.)
•
Static operation
•
TTL compatible I/O
•
Three-state outputs
•
Single +5 V power supply
•
JEDEC standard EPROM pinout (DIP)
•
Packages:
40-pin, 600-mil DIP
40-pin, 525-mil SOP
44-pin, 650-mil QFJ (PLCC)
DESCRIPTION
The LH531024 is a mask-programmable ROM
organized as 65,536
×
16 bits. It is fabricated using
silicon-gate CMOS process technology.
NC
CE
D
15
D
14
D
13
D
12
D
11
D
10
D
9
D
8
GND
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
OE
40-PIN DIP
40-PIN SOP
CMOS 1M (64K
×
16) MROM
PIN CONNECTIONS
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
CC
NC
NC
A
15
A
14
A
13
A
12
A
11
A
10
A
9
GND
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
531024-1
Figure 1. Pin Connections for DIP and
SOP Packages
44-PIN PLCC
TOP VIEW
D
12
D
11
D
10
D
9
D
8
GND
NC
D
7
D
6
D
5
D
4
7
8
9
10
11
12
13
14
15
16
D
13
D
14
D
15
CE
NC
NC
V
CC
NC
NC
A
15
A
14
6 5 4 3 2 1 44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
A
13
A
12
A
11
A
10
A
9
GND
NC
A
8
A
7
A
6
A
5
29
17
18 19 20 21 22 23 24 25 26 27 28
D
3
D
2
D
1
D
0
OE
NC
A
0
A
1
A
2
A
3
A
4
531024-2
Figure 2. Pin Connections for QFJ
(PLCC) Package
1
LH531024
CMOS 1M MROM
A
15
37
A
14
36
A
13
35
A
12
34
A
11
33
A
10
32
A
9
31
A
8
29
A
7
28
A
6
27
A
5
26
A
4
25
A
3
24
A
2
23
A
1
22
A
0
21
MEMORY
MATRIX
(65,536 x 16)
ADDRESS DECODER
ADDRESS BUFFER
COLUMN SELECTOR
CE 2
CE
BUFFER
TIMING
GENERATOR
SENSE AMPLIFIER
OE 20
OE
BUFFER
OUTPUT BUFFER
40
V
CC
11 30
GND
19 18 17 16 15 14 13 12 10 9 8 7 6 5 4 3
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
D
10
D
11
D
12
D
13
D
14
D
15
531024-3
NOTE:
Pin numbers apply to the 40-pin DIP or SOP.
Figure 3. LH531024 Block Diagram
PIN DESCRIPTION
SIGNAL
PIN NAME
SIGNAL
PIN NAME
A
0
– A
15
D
0
– D
15
CE
Address input
Data output
Chip Enable input
OE
V
CC
GND
Output enable input
Power supply (+5 V)
Ground
2
CMOS 1M MROM
LH531024
A
15
41
A
14
40
A
13
39
A
12
38
A
11
37
A
10
36
A
9
35
A
8
32
A
7
31
A
6
30
A
5
29
A
4
28
A
3
27
A
2
26
A
1
25
A
0
24
MEMORY
MATRIX
(65,536 x 16)
ADDRESS DECODER
ADDRESS BUFFER
COLUMN SELECTOR
CE 3
CE
BUFFER
TIMING
GENERATOR
SENSE AMPLIFIER
OE 22
OE
BUFFER
OUTPUT BUFFER
44
V
CC
NOTE:
Pin numbers apply to the 44-pin QFJ.
12 34
GND
21 20 19 18 17 16 15 14 11 10 9 8 7 6 5 4
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
D
10
D
11
D
12
D
13
D
14
D
15
531024-4
Figure 4. LH531024 Block Diagram
3
LH531024
CMOS 1M MROM
TRUTH TABLE
CE
OE
D
0
– D
15
SUPPLY CURRENT
NOTE
H
L
L
NOTE:
1. X = H or L.
X
H
L
High-Z
D
0
– D
15
Standby (I
SB
)
Operating (I
CC
)
1
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNIT
Supply voltage
Input voltage
Output voltage
Operating temperature
Storage temperature
V
CC
V
IN
V
OUT
Topr
Tstg
–0.3 to +7.0
–0.3 to V
CC
+0.3
–0.3 to V
CC
+0.3
0 to +70
– 65 to +150
V
V
V
°C
°C
RECOMMENDED OPERATING CONDI-
TIONS (T
A
= 0°C to +70°C)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Supply voltage
V
CC
4.5
5.0
5.5
V
DC CHARACTERISTICS (V
CC
= 5 V
±10%,
T
A
= 0°C to +70°C)
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
NOTE
Input ‘Low’ voltage
Input ‘High’ voltage
Output ‘Low’ voltage
Output ‘High’ voltage
Input leakage current
Output leakage current
V
IL
V
IH
V
OL
V
OH
| I
LI
|
| I
LO
|
I
CC1
I
CC2
I
CC3
I
CC4
I
SB1
I
SB2
C
IN
C
OUT
I
OL
= 2.0 mA
I
OH
= –400
µA
V
IN
= 0 V to V
CC
V
OUT
= 0 V to V
CC
t
RC
= 100 ns
t
RC
= 1
µs
t
RC
= 100 ns
t
RC
= 1
µs
CE = V
IH
CE = V
CC
– 0.2 V
f = 1 MHz
T
A
= 25°C
–0.3
2.2
2.4
0.8
V
CC
+ 0.3
0.4
10
10
75
65
70
60
3
100
10
10
V
V
V
V
µA
µA
mA
mA
mA
mA
mA
µA
pF
pF
3
1
2
Operating current
Standby current
Input capacitance
Output capacitance
NOTES:
1. CE/OE = V
IH
2. V
IN
= V
IH
or V
IL
, CE = V
IL
, outputs open
3. V
IN
= (V
CC
– 0.2 V) or 0.2 V, CE = 0.2 V, outputs open
4
CMOS 1M MROM
LH531024
AC CHARACTERISTICS (V
CC
= 5 V
±10%,
T
A
= 0°C to +70°C)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTE
Read cycle time
Address access time
Chip enable access time
Output enable delay time
Output hold time
CE to output in High-Z
OE to output in High-Z
t
RC
t
AA
t
ACE
t
OE
t
OH
t
CHZ
t
OHZ
100
100
100
50
5
50
50
ns
ns
ns
ns
ns
ns
ns
1
NOTE:
1. This is the time required for the output to become high-imped-
ance.
AC TEST CONDITIONS
PARAMETER
RATING
Input voltage amplitude
Input signal rise time
Input/output reference level
Output load condition
0.4 V to 2.6 V
10 ns
1.5 V
1TTL +100 pF
CAUTION
To stabilize the power supply, it is recommended that
a high-frequency bypass capacitor be connected be-
tween the V
CC
pin and the GND pin.
t
RC
A
0
- A
15
t
AA
(NOTE)
CE
t
ACE
(NOTE)
OE
t
OE
(NOTE)
t
OH
t
OHZ
t
CHZ
D
0
- D
15
DATA VALID
NOTE:
Data becomes valid after the intervals, t
AA
, t
ACE
, and t
OE
, from address
input, chip enable, and output enable, respectively have been met.
531024-5
Figure 5. Timing Diagram
5
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