LH530800A
FEATURES
•
131,072 words
×
8 bit organization
•
Access time: 150 ns (MAX.)
•
Power consumption:
Operating: 192.5 mW (MAX.)
Standby: 550
µW
(MAX.)
•
Static operation
•
TTL compatible I/O
•
Three-state outputs
•
Single +5 V power supply
•
Packages:
32-pin, 600-mil DIP
32-pin, 525-mil SOP
32-pin, 450-mil QFJ (PLCC)
•
JEDEC standard EPROM pinout (DIP)
DESCRIPTION
The LH530800A is a mask-programmable ROM
organized as 131,072
×
8 bits (1,048,576 bits). It is fab-
ricated using silicon-gate CMOS process technology.
32-PIN DIP
32-PIN SOP
CMOS 1M (128K
×
8) MROM
PIN CONNECTIONS
TOP VIEW
NC
A
16
A
15
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
0
D
1
D
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
NC
NC
A
14
A
13
A
8
A
9
A
11
OE/OE
A
10
CE
D
7
D
6
D
5
D
4
D
3
530800A-1
Figure 1. Pin Connections for DIP and
SOP Packages
32-PIN QFJ
TOP VIEW
V
CC
A
12
A
15
A
16
NC
NC
4
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
0
5
6
7
8
9
10
11
12
13
3
2
1
32 31 30
29
28
27
26
25
24
23
22
21
A
14
A
13
A
8
A
9
A
11
OE/OE
A
10
CE
D
7
14 15 16 17 18 19 20
D
1
GND
D
2
D
3
D
4
D
5
D
6
NC
530800A-7
Figure 2. Pin Connections for QFJ
(PLCC) Package
1
LH530800A
CMOS 1M Mask-Programmable ROM
A
16
2
A
15
3
A
14
29
A
10
23
A
9
26
A
8
27
A
7
5
A
6
6
A
5
7
A
4
8
A
3
9
A
2
10
A
1
11
A
0
12
ADDRESS DECODER
ADDRESS BUFFER
A
13
28
A
12
4
A
11
25
MEMORY
MATRIX
(131,072 x 8)
COLUMN SELECTOR
SENSE AMPLIFIER
CE 22
CE
BUFFER
TIMING
GENERATOR
OUTPUT BUFFER
OE/OE 24
OE
BUFFER
32
16
V
CC
GND
13
D
0
14
D
1
15
D
2
17
D
3
18
D
4
19
D
5
20
D
6
21
D
7
530800A-2
Figure 3. LH530800A Block Diagram
PIN DESCRIPTION
SIGNAL
PIN NAME
NOTE
SIGNAL
PIN NAME
NOTE
A
0
- A
16
D
0
- D
7
CE
OE/OE
Address input
Data Output
Chip enable input
Output enable input
1
1
V
CC
GND
NC
Power supply (+5 V)
Ground
No connection
NOTE:
1. Active level of OE/OE is mask-programmable.
TRUTH TABLE
CE
OE/OE
MODE
D
0
- D
7
SUPPLY CURRENT
NOTE
H
L
L
NOTE:
1. X = H or L.
X
L/H
H/L
Non selected
Non selected
Selected
High-Z
High-Z
D
OUT
Standby (I
SB
)
Operating (I
CC
)
Operating (I
CC
)
1
2
CMOS 1M Mask-Programmable ROM
LH530800A
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNIT
Supply voltage
Input voltage
Output voltage
Operating temperature
Storage temperature
V
CC
V
IN
V
OUT
Topr
Tstg
–0.3 to +7.0
–0.3 to V
CC
+0.3
–0.3 to V
CC
+0.3
0 to +70
–65 to +150
V
V
V
°C
°C
RECOMMENDED OPERATING CONDI-
TIONS (T
A
= 0 to +70°C)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Supply voltage
V
CC
4.5
5.0
5.5
V
DC CHARACTERISTICS (V
CC
= 5 V
±10%,
T
A
= 0 to +70°C)
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
NOTE
Input ‘Low’ voltage
Input ‘High’ voltage
Output ‘Low’ voltage
Output ‘High’ voltage
Input leakage current
Output leakage current
V
IL
V
IH
V
OL
V
OH
| I
LI
|
| I
LO
|
I
CC1
I
CC2
I
CC3
I
CC4
I
SB1
I
SB2
C
IN
C
OUT
I
OL
= 2.0 mA
I
OH
= –400
µA
V
IN
= 0 V to V
CC
V
OUT
= 0 V to V
CC
t
RC
= 150 ns
t
RC
= 1
µs
t
RC
= 150 ns
t
RC
= 1
µs
CE = V
IH
CE = V
CC
- 0.2 V
f = 1 MHz
T
A
= 25°C
–0.3
2.2
2.4
0.8
V
CC
+ 0.3
0.4
10
10
35
25
30
20
2
100
10
10
V
V
V
V
µA
µA
mA
mA
mA
µA
pF
pF
1
2
3
Operating current
Standby current
Input capacitance
Output capacitance
NOTES:
1. CE/OE = V
IH
or OE = V
IL
2. V
IN
= V
IH
or V
IL
, CE = V
IL
, outputs open
3. V
IN
= (V
CC
- 0.2 V) or 0.2 V, CE = 0.2 V, outputs open
AC CHARACTERISTICS (V
CC
= 5 V
±10%,
T
A
= 0 to +70°C)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTE
Read cycle time
Address access time
Chip enable time
Output enable time
Output hold time
CE to output in High-Z
OE to output in High-Z
t
RC
t
AA
t
ACE
t
OE
t
OH
t
CHZ
t
OHZ
150
150
150
70
5
70
70
ns
ns
ns
ns
ns
ns
ns
1
NOTE:
1. This is the time required for the output to become high-imped-
ance.
3
LH530800A
CMOS 1M Mask-Programmable ROM
AC TEST CONDITIONS
PARAMETER
RATING
Input voltage amplitude
Input rise/fall time
Input reference level
Output reference level
Output load condition
0.6 V to 2.4 V
10 ns
1.5 V
0.8 V and 2.2 V
1TTL +100 pF
t
RC
A
0
- A
16
t
AA
(NOTE)
CE
t
ACE
(NOTE)
OE
OE
t
OE
(NOTE)
t
OHZ
t
CHZ
D
0
- D
7
DATA VALID
t
OH
NOTE:
Data becomes valid after t
AA
, t
ACE
, and t
OE
from address
input, chip enable and output enable, respectively have been met.
530800A-3
Figure 4. Timing Diagram
4
CMOS 1M Mask-Programmable ROM
LH530800A
PACKAGE DIAGRAMS
32DIP (DIP032-P-0600)
32
17
DETAIL
13.45 [0.530]
12.95 [0.510]
1
41.30 [1.626]
40.70 [1.602]
16
0.30 [0.012]
0.20 [0.008]
0° TO 15°
4.50 [0.177]
4.00 [0.157]
5.20 [0.205]
5.00 [0.197]
3.50 [0.138]
3.00 [0.118]
2.54 [0.100]
TYP.
0.51 [0.020] MIN.
0.60 [0.024]
0.40 [0.016]
MAXIMUM LIMIT
MINIMUM LIMIT
15.24 [0.600]
TYP.
DIMENSIONS IN MM [INCHES]
32DIP
32-pin, 600-mil DIP
32SOP (SOP032-P-0525)
1.27 [0.050]
TYP.
1.40 [0.055]
17
0.50 [0.020]
0.30 [0.012]
32
11.50 [0.453]
11.10 [0.437]
14.50 [0.571]
13.70 [0.539]
12.50 [0.492]
1
20.80 [0.819]
20.40 [0.803]
16
1.40 [0.055]
0.20 [0.008]
0.10 [0.004]
0.15 [0.006]
1.275 [0.050]
2.90 [0.114]
2.50 [0.098]
0.20 [0.008]
0.00 [0.000]
1.275 [0.050]
MAXIMUM LIMIT
MINIMUM LIMIT
DIMENSIONS IN MM [INCHES]
32SOP
32-pin, 525-mil SOP
5
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