LH532000B
FEATURES
•
262,144 words
×
8 bit organization
(Byte mode)
131,072 words
×
16 bit organization
(Word mode)
•
BYTE input pin selects bit configuration
•
Access times: 120/150 ns (MAX.)
•
Low-power consumption:
Operating: 275 mW (MAX.)
Standby: 550
µW
(MAX.)
•
Programmable OE/OE and OE
1
/OE
1
/DC
•
Static operation
•
TTL compatible I/O
•
Three-state outputs
•
Single +5 V power supply
•
Packages:
40-pin, 600-mil DIP
40-pin, 525-mil SOP
48-pin, 12
×
18 mm
2
TSOP (Type I)
• ×16
word-wide pinout
DESCRIPTION
The LH532000B is a 2M-bit mask-programmable
ROM with two programmable memory organizations,
byte and word modes. It is fabricated using silicon-gate
CMOS process technology.
CMOS 2M (256K
×
8/128K
×
16) MROM
PIN CONNECTIONS
40-PIN DIP
40-PIN SOP
TOP VIEW
OE
1
/OE
1
/DC
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
CE
GND
OE/OE
D
0
D
8
D
1
D
9
D
2
D
10
D
3
D
11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
48
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
BYTE
GND
D
15
/A
-1
(LSB)
D
7
D
14
D
6
D
13
D
5
D
12
D
4
V
CC
532000B-1
Figure 1. Pin Connections for DIP and
SOP Packages
1
LH532000B
CMOS 2M MROM
48-PIN TSOP (Type I)
BYTE
A
16
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
NC
GND
NC
NC
OE
1
/OE
1
/DC
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
CE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GND
GND
D
15
/A
-1
D
7
D
14
D
6
D
13
D
5
D
12
D
4
V
CC
V
CC
GND
D
11
D
3
D
10
D
2
D
9
D
1
D
8
D
0
OE/OE
GND
GND
NOTE:
Reverse bend available on request.
532000B-5
Figure 2. Pin Connections for TSOP Package
2
CMOS 2M MROM
LH532000B
ADDRESS DECODER
ADDRESS BUFFER
35
36
37
38
39
40
2
3
5
6
7
8
DATA SELECTOR/OUTPUT BUFFER
A
16
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
4
A
3
A
2
A
1
32
33
34
MEMORY
MATRIX
(262,144 x 8)
(131,072 x 16)
29 D
15
27 D
14
25 D
13
23 D
12
20 D
11
18 D
10
16 D
9
14 D
8
28 D
7
26 D
6
24 D
5
22 D
4
19 D
3
17 D
2
15 D
1
13 D
0
A
5
4
COLUMN SELECTOR
A
0
9
CE 10
CE
BUFFER
TIMING
GENERATOR
SENSE AMPLIFIER
OE
1
/OE
1
/DC 1
OE/OE 12
OE
BUFFER
BYTE 31
BYTE/WORD
SWITCHOVER
CIRCUIT
ADDRESS
BUFFER
29
A
-1
NOTE:
Pin numbers apply to the 40-pin DIP or SOP.
21
V
CC
11
30
GND
532000B-2
Figure 3. LH532000B Block Diagram
PIN DESCRIPTION
SIGNAL
PIN NAME
NOTE
SIGNAL
PIN NAME
NOTE
A
–1
A
0
– A
16
D
0
– D
15
CE
OE/OE
Address input (BYTE mode)
Address input
Data output
Chip enable input
Output enable input
1
1
2
OE
1
/OE
1
/DC
BYTE
V
CC
GND
Output enable input or
Don’t care
Byte/word mode switch
Power supply (+5 V)
Ground
2
NOTES:
1. D
15
/A
–1
pin becomes LSB address input (A
–1
) when the bit configuration is set in byte mode,
and data output (D
15
) when in word mode. BYTE input pin selects bit configuration.
2. The active levels of OE/OE and OE
1
/OE
1
/DC are mask-programmable.
Selecting DC allows the outputs to be active for both high and low levels applied to this pin.
It is recommended to apply either a HIGH or a LOW to the DC pin.
3
LH532000B
CMOS 2M MROM
TRUTH TABLE
CE
OE/OE
OE
1
/OE
1
BYTE
A
–1
(D
15
)
DATA OUTPUT
D
0
– D
7
D
8
– D
15
ADDRESS INPUT
LSB
MSB
SUPPLY CURRENT
H
L
L
L
L
L
X
L/H
X
H/L
H/L
H/L
X
X
L/H
H/L
H/L
H/L
X
X
X
H
L
L
X
X
X
Input
inhibit
L
H
High-Z
High-Z
High-Z
D
0
– D
7
D
0
– D
7
D
8
– D
15
High-Z
High-Z
High-Z
D
8
– D
15
High-Z
High-Z
–
–
–
A
0
A
–1
A
–1
–
–
–
A
16
A
16
A
16
Standby (I
SB
)
Operating (I
CC
)
Operating (I
CC
)
Operating (I
CC
)
Operating (I
CC
)
Operating (I
CC
)
NOTE:
1. X = H or L, High-Z = High-impedance.
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNIT
Supply voltage
Input voltage
Output voltage
Operating temperature
Storage temperature
V
CC
V
IN
V
OUT
Topr
Tstg
– 0.3 to +7.0
– 0.3 to V
CC
+ 0.3
– 0.3 to V
CC
+ 0.3
0 to +70
– 65 to +150
V
V
V
°C
°C
RECOMMENDED OPERATING CONDITIONS (T
A
= 0 to +70°C)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Supply voltage
V
CC
4.5
5.0
5.5
V
DC CHARACTERISTICS (V
CC
= 5 V
±10%,
T
A
= 0 to +70°C)
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
NOTE
Input ‘Low’ voltage
Input ‘High’ voltage
Output ‘Low’ voltage
Output ‘High’ voltage
Input leakage current
Output leakage current
V
IL
V
IH
V
OL
V
OH
| I
LI
|
| I
LO
|
I
CC1
I
CC2
I
CC3
I
CC4
I
SB1
I
SB2
C
IN
C
OUT
I
OL
= 2.0 mA
I
OH
= –400
µA
V
IN
= 0 V to V
CC
V
OUT
= 0 V to V
CC
t
RC
= t
RC
(MIN.)
t
RC
= 1
µs
t
RC
= t
RC
(MIN.)
t
RC
= 1
µs
CE = V
IH
CE = V
CC
- 0.2 V
f = 1 MHz
T
A
= 25°C
– 0.3
2.2
2.4
0.8
V
CC
+ 0.3
0.4
10
10
50
45
45
40
3
100
10
10
V
V
V
V
µA
µA
mA
mA
mA
µA
pF
pF
1
2
3
Operating current
Standby current
Input capacitance
Output capacitance
NOTES:
1. OE/OE
1
= V
IL
, CE/OE/OE
1
= V
IH
2. V
IN
= V
IH
or V
IL
, CE = V
IL
, outputs open
3. V
IN
= (V
CC
- 0.2 V) or 0.2 V, CE = 0.2 V, outputs open
4
CMOS 2M MROM
LH532000B
AC CHARACTERISTICS (V
CC
= 5 V
±10%,
T
A
= 0 to +70°C)
PARAMETER
SYMBOL
MIN.
120 ns
MAX.
MIN.
150 ns
MAX.
UNIT
NOTE
Read cycle time
Address access time
Chip enable access time
Output enable delay time
Output hold time
CE to output in High-Z
OE to output in High-Z
t
RC
t
AA
t
ACE
t
OE
t
OH
t
CHZ
t
OHZ
120
120
120
55
5
55
55
150
150
150
70
10
70
70
ns
ns
ns
ns
ns
ns
ns
1
NOTE:
1. This is the time required for the output to become high-impedance.
AC TEST CONDITIONS
PARAMETER
RATING
Input voltage amplitude
Input rise/fall time
Input reference level
Output reference level
Output load condition
0.6 V to 2.4 V
10 ns
1.5 V
0.8 V and 2.2 V
1TTL +100 pF
CAUTION
To stabilize the power supply, it is recommended that a high-frequency bypass capacitor be connected between
the V
CC
pin and the GND pin.
t
RC
(NOTE 2)
A-
1
- A
16
(A
0
- A
16
)
t
AA
(NOTE 1)
CE
t
ACE
OE/OE
1
OE/OE
1
t
OE
(NOTE 1)
(NOTE 2)
D
0
- D
7
(D
0
- D
15
)
DATA VALID
t
OH
NOTES:
1. Data becomes valid after t
AA
, t
ACE
, and t
OE
from address
input, chip enable or output enable, respectively have been met.
2. Applied to byte mode. Signals in parentheses apply to word mode.
t
OHZ
t
CHZ
532000B-3
Figure 4. Timing Diagram
5
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