LH5324C00
FEATURES
•
1,572,864
×
16 bit organization
•
Access time: 120 ns (MAX.)
•
Supply current:
– Operating: 80 mA (MAX.)
– Standby: 100
µA
(MAX.)
•
TTL compatible I/O
•
Three-state output
•
Single +5 V Power supply
•
Static operation
•
When the address input at both A
19
and
A
20
is high level, outputs become high
impedance irrespective of CE or OE.
•
Package:
42-pin, 600-mil DIP
•
Others:
– Non programmable
– Not designed or rated as radiation
hardened
– CMOS process (P type silicon
substrate)
DESCRIPTION
The LH5324C00 is a 24M-bit mask-programmable
ROM organized as 1,572,864
×
16 bits. It is fabricated
using silicon-gate CMOS process technology.
42-PIN DIP
CMOS 24M (1.5M
×
16) MROM
PIN CONNECTIONS
TOP VIEW
A
18
A
17
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
CE
GND
OE
D
0
D
8
D
1
D
9
D
2
D
10
D
3
D
11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
A
19
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
20
GND
D
15
D
7
D
14
D
6
D
13
D
5
D
12
D
4
V
CC
5324C00-1
Figure 1. Pin Connections
1
LH5324C00
CMOS 24M (1.5M x 16) MROM
A
20
32
A
19
42
A
18
1
A
17
2
A
16
33
A
15
34
A
14
35
MEMORY
MATRIX
(1,572,864 x 16)
30 D
15
28 D
14
ADDRESS BUFFER
A
10
39
A
9
40
A
8
41
A
7
3
A
6
4
A
5
5
A
4
A
3
A
2
6
7
8
DATA SELECTOR/OUTPUT BUFFER
A
13
36
A
12
37
A
11
38
ADDRESS DECODER
26 D
13
24 D
12
21 D
11
19
17
15
29
D
10
D
9
D
8
D
7
27 D
6
25 D
5
23 D
4
20 D
3
18 D
2
16 D
1
14 D
0
COLUMN SELECTOR
A
1
9
A
0
10
CE 11
CE
BUFFER
TIMING
GENERATOR
SENSE AMPLIFIER
OE 13
OE
BUFFER
22
V
CC
12 31
GND
5324C00-2
Figure 2. LH5324C00 Block Diagram
PIN DESCRIPTION
SIGNAL
PIN NAME
SIGNAL
PIN NAME
A
0
- A
20
D
0
- D
15
CE
Address input
Data output
Chip enable input
OE
V
CC
GND
Output enable input
Power supply (+5 V)
Ground
2
CMOS 24M (1.5M x 16) MROM
LH5324C00
TRUTH TABLE
CE
OE
A
0
- A
18
A
19
A
20
DATA
OUTPUT
D
0
- D
15
SUPPLY
CURRENT
H
L
L
L
L
L
X
H
L
L
L
L
X
X
X
X
X
X
X
X
L
L
H
H
X
X
L
H
L
H
High-Z
High-Z
Output
Output
Output
High-Z
Standby (I
SB
)
Operating (I
CC
)
Operating (I
CC
)
Operating (I
CC
)
Operating (I
CC
)
Operating (I
CC
)
NOTES:
1. X = Don’t care; High-Z = High-impedance
2. When the address inputs become HIGH to both A
19
and A
20
, the data does not exist in this address area,
the data outputs become "High Impedance".
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNIT
Supply voltage
Input voltage
Output voltage
Operating temperature
Storage temperature
V
CC
V
IN
V
OUT
T
OPR
T
STG
-0.3 to +7.0
-0.3 to V
CC
+ 0.3
-0.3 to V
CC
+ 0.3
0 to +70
-65 to +150
V
V
V
°C
°C
RECOMMENDED OPERATING CONDITIONS (T
A
= 0 to +70°C)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Supply voltage
V
CC
4.5
5.0
5.5
V
DC ELECTRICAL CHARACTERISTICS (V
CC
= 5 V
±
10%, T
A
= 0 to +70°C)
PARAMETER
SYMBOL
CONDITIONS
MIN.
MAX.
UNIT
NOTE
Input ‘High’ voltage
Input ‘Low’ voltage
Output ‘High’ voltage
Output ‘Low’ voltage
Input leakage current
Output leakage current
Operating current
V
IH
V
IL
V
OH
V
OL
| I
LI
|
| I
LO
|
I
CC1
I
CC2
I
OH
= -400
µA
I
OL
= 2.0 mA
V
IN
= 0 V to V
CC
V
OUT
= 0 V to V
CC
t
RC
= 120 ns
t
RC
= 1
µs
CE = V
IH
CE = V
CC
- 0.2 V
f = 1 MHz, t
A
= 25°C
2.2
-0.3
2.4
V
CC
+ 0.3
0.8
0.4
10
10
80
70
2
100
10
10
V
V
V
V
µA
µA
mA
mA
µA
pF
pF
1
2
Standby current
Input capacitance
Output capacitance
I
SB1
I
SB2
C
IN
C
OUT
NOTES:
1. CE = V
IH
, OE = V
IH
2. V
IN
= V
IH
or V
IL
, CE = V
IL
, output is open
3
LH5324C00
CMOS 24M (1.5M x 16) MROM
AC ELECTRICAL CHARACTERISTICS (V
CC
= +5 V
±
10%, T
A
= 0 to +70°C)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
NOTE
Read cycle time
Address access time
Chip enable access time
Output enable delay time
Output hold time
t
RC
t
AA
t
ACE
t
OE
t
OH
t
CHZ
120
0
120
120
60
50
50
60
ns
ns
ns
ns
ns
ns
ns
ns
Output floating time
t
OHZ
t
AHZ
1
NOTE:
1. Determined by the time for the output to be opened. (Irrespective of output voltage)
AC TEST CONDITIONS
PARAMETER
RATING
Input voltage amplitude
Input signal rise time
Input signal fall time
Input reference level
Output reference level
Output load condition
0.6 V to 2.4 V
10 ns
10 ns
1.5 V
1.5 V
1TTL + 100 pF
NOTE:
It is recommended that a decoupling capacitor be connected between V
CC
and GND-Pin.
4
CMOS 24M (1.5M x 16) MROM
LH5324C00
t
RC
A
0
- A
20
t
AA
(NOTE)
CE
t
ACE
(NOTE)
OE
t
OE
(NOTE)
t
OH
HI-Z
t
OHZ
t
CHZ
D
0
- D
15
HI-Z
DATA VALID
NOTE:
The output data becomes valid when the last
intervals, t
AA
, t
ACE
, or t
OE
, have concluded.
HI-Z = High Impedance.
5324C00-3
Figure 3. Byte Mode
A
0
- A
18
A
19
, A
20
CE
t
CHZ
OE
t
OHZ
t
AHZ
HI-Z
HI-Z
D
0
- D
15
DATA VALID
NOTE:
The output data becomes valid when the last
intervals, t
AA
, t
ACE
, or t
OE
, have concluded.
HI-Z = High impedance.
5324C00-4
Figure 4. Word Mode
5
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